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TECHNICAL MANUAL
L80227 10BASE-T/ 100BASE-TX Ethernet PHY
October 2002
(R)
This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an ofcer of LSI Logic Corporation. DB14-000139-02, Third Edition (October 2002) This document describes revision/release 2 of LSI Logic Corporation's 10BASE-T/100BASE-TX Ethernet PHY and will remain the ofcial reference source for all revisions/releases of this product until rescinded by an update. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT LSI Logic and the LSI Logic logo design are trademarks or registered trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. MT To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales ofces, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesofces.html
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Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the L80227 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY). It contains a complete functional description for the device and includes complete physical and electrical specications for the product.
Audience This document assumes that you have some familiarity with Ethernet devices and related support devices. The people who benet from this book are: Engineers and managers who are evaluating the device for possible use in a system Engineers who are designing the device into a system
Organization This document has the following chapters: Chapter 1, Introduction, describes the device in general terms and gives a block diagram and lists the device features. Chapter 2, Functional Description, describes each of the internal blocks in the device in some detail. Chapter 3, Signal Descriptions, lists and describes the device input and output signals. Chapter 4, Registers, gives a register summary and describes each of the bits in each register. Chapter 5, Management Interface, describes the device Management Interface, which allows the registers to be read and written.
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
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Chapter 6, Specications, lists the AC and DC characteristics and gives typical timing parameters. Appendix A, Application Information, gives practical guidelines for incorporating the device into a design.
Abbreviations Used in This Manual Below is a list of abbreviations used throughout this manual.
100BASE-T 10BASE-T 4B5B CLK CRC CRS CSMA CWRD DA ECL EOF ESD FCS FDX FEF FIFO FLP FX HDX HIZ I/G IETF IPG IREF L/T LSB MIB MLT3 ms MSB mV NLP NRZI NRZ OP PCB pF 100 Mbit/s Twisted-Pair Ethernet 10 Mbit/s Twisted-Pair Ethernet 4-Bit 5-Bit Clock Cyclic Redundancy Check Carrier Sense Carrier Sense Multiple Access Codeword Destination Address Emitter-Coupled Logic End of Frame End of Stream Delimiter Frame Check Sequence Full-Duplex Far End Fault First In - First Out Fast Link Pulse Fiber Half-Duplex High Impedance Individual/Group Internet Engineering Task Force Inter-Packet Gap Reference Current Length and Type Least-Signicant Bit Management Information Base Multi-Level Transmission (3 levels) millisecond Most-Signicant Bit millivolt Normal Link Pulse Non-Return to Zero Inverted Non-Return to Zero Opcode Printed Circuit Board picofarad
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Preface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
PRE R/LH R/LHI R/LL R/LLI R/LT R/LTI R/WSC RFC RJ-45 RMON SA SFD SNMP SOI SSD STP TP H P UTP
Preamble Read Latched High Read Latched High with Interrupt Read Latched Low Read Latched Low with Interrupt Read Latched Transition Read Latched Transition with Interrupt Read/Write Self Clearing Request for Comments Registered Jack-45 Remote Monitoring Start Address or Station Address Start of Frame Delimiter Simple Network Management Protocol Start of Idle Start of Stream Delimiter Shielded Twisted Pair Twisted Pair microhenry microprocessor Unshielded Twisted Pair
Conventions Used in This Manual The rst time a word or phrase is dened in this manual, it is italicized. The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prex "0x" --for example, 0x32CF. Binary numbers are indicated by the prex "0b" --for example, 0b0011.0010.1100.1111.
Preface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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Preface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1 Introduction 1.1 1.2 Chapter 2 Functional Description 2.1 2.2 Overview Features 1-1 1-3
2.3
2.4
2.5
Device Differences Overview 2.2.1 Channel Operation 2.2.2 Data Paths Block Diagram Description 2.3.1 Oscillator and Clock 2.3.2 Controller Interface 2.3.3 Encoder 2.3.4 Decoder 2.3.5 Scrambler 2.3.6 Descrambler 2.3.7 Twisted-Pair Transmitters 2.3.8 Twisted-Pair Receiver 2.3.9 Clock and Data Recovery 2.3.10 Link Integrity and AutoNegotiation 2.3.11 Link Indication 2.3.12 Collision 2.3.13 LED Drivers Start of Packet 2.4.1 100 Mbits/s 2.4.2 10 Mbits/s End of Packet
2-2 2-3 2-3 2-3 2-8 2-8 2-9 2-12 2-13 2-14 2-14 2-15 2-18 2-21 2-22 2-26 2-26 2-28 2-30 2-30 2-31 2-31
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
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2.6
2.7
2.8 2.9 2.10 Chapter 3 Signal Descriptions 3.1 3.2 3.3 3.4 3.5 3.6 Chapter 4 Registers 4.1 4.2 4.3
2.5.1 100 Mbits/s 2.5.2 10 Mbits/s Full-/Half-Duplex Mode 2.6.1 Forcing Full-/Half-Duplex Operation 2.6.2 Full/Half Duplex Indication 2.6.3 Loopback 10/100 Mbits/s Selection 2.7.1 Forcing 10/100 Mbits/s Operation 2.7.2 Autoselecting 10/100 Mbits/s Operation 2.7.3 10/100 Mbits/s Indication Jabber Reset Receive Polarity Correction
2-32 2-32 2-33 2-34 2-34 2-34 2-35 2-35 2-35 2-36 2-36 2-36 2-37
Media Interface Signals Controller Interface Signals (MII) Management Interface (MI)/LED Signals LED Signals Miscellaneous Signals Power Supply
3-2 3-3 3-4 3-6 3-7 3-8
Bit Types MI Serial Port Register Summary Registers 4.3.1 Control Register (Register 0) 4.3.2 Status Register (Register 1) 4.3.3 PHY ID 1 Register (Register 2) 4.3.4 PHY ID 2 Register (Register 3) 4.3.5 AutoNegotiation Advertisement Register (Register 4) 4.3.6 AutoNegotiation Remote End Capability Register (Register 5) 4.3.7 Conguration Register (Register 17)
4-1 4-3 4-5 4-5 4-7 4-9 4-10 4-11 4-13 4-15
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Contents
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4.3.8 Chapter 5 Management Interface 5.1 5.2 5.3 5.4 Chapter 6 Specications 6.1 6.2 6.3
Channel Status Output 0 Register (Register 18)
4-17
Signal Description General Operation Frame Structure Register Structure
5-1 5-2 5-4 5-5
6.4
6.5 Appendix A Application Information A.1 A.2 A.3 A.4 A.5 A.6
Absolute Maximum Ratings Electrical Characteristics 6.2.1 Twisted-Pair DC Characteristics AC Electrical Characteristics 6.3.1 25 MHz Input/Output Clock Timing Characteristics 6.3.2 Transmit Timing Characteristics 6.3.3 Receive Timing Characteristics 6.3.4 Collision and JAM Timing Characteristics 6.3.5 Link Pulse Timing Characteristics 6.3.6 Jabber Timing Characteristics 6.3.7 MI Serial Port Timing Characteristics Pinouts and Package Drawings 6.4.1 L80227 Pinouts 6.4.2 L80227 Pin Layout Mechanical Drawing
6-1 6-2 6-3 6-6 6-7 6-7 6-11 6-16 6-19 6-25 6-26 6-27 6-27 6-33 6-34
Example Schematics TP Transmit Interface TP Receive Interface TP Transmit Output Current Set Transmitter Droop MII Controller Interface A.6.1 Clocks A.6.2 Output Drive
A-1 A-5 A-6 A-7 A-8 A-8 A-8 A-9
Contents
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A.6.3 MII Disable A.6.4 Receive Output Enable A.7 Repeater Applications A.7.1 MII Based Repeaters A.7.2 Clocks A.8 Serial Port A.8.1 Serial Port Addressing A.9 Oscillator A.10 LED Drivers A.11 Power Supply Decoupling Customer Feedback
A-10 A-11 A-11 A-11 A-11 A-12 A-12 A-14 A-15 A-15
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Contents
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figures 1.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.1 5.1 5.2 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 A.1 A.2 A.3 A.4 Top Level Block Diagram L80227 Device Block Diagram 100BASE-TX and 10BASE-T Frame Format MII Frame Format TP Output Voltage Template TP Input Voltage Template (10 Mbits/s) Link Pulse Output Voltage Template (10 Mbits/s) NLP vs FLP Link Pulse SOI Output Voltage Template (10 Mbits/s) Device Logic Diagram MI Serial Port Frame Timing Diagram MI Serial Frame Structure 25 MHz Output Timing Transmit Timing (100 Mbits/s) Transmit Timing (10 Mbits/s) Receive Timing, Start of Packet (100 Mbits/s) Receive Timing, End of Packet (100 Mbits/s) Receive Timing, Start of Packet (10 Mbits/s) Receive Timing, End of Packet (10 Mbits/s) RX_EN Timing Collision Timing, Receive (100 Mbits/s) Collision Timing, Receive (10 Mbits/s) Collision Timing, Transmit (100 Mbits/s) Collision Timing, Transmit (10 Mbits/s) Collision Test Timing NLP Link Pulse Timing FLP Link Pulse Timing Jabber Timing MI Serial Port Timing L80227 64-Pin LQFP, Top View 64-Pin LQFP Package Drawing Typical Network Interface Adapter Card Schematic Using the L80227 Typical Switching Port Schematic Using L80227 Typical External PHY Schematic Using L80227 MII Output Driver Characteristics 1-2 2-4 2-5 2-6 2-17 2-19 2-23 2-24 2-33 3-2 5-3 5-4 6-7 6-9 6-10 6-13 6-13 6-14 6-15 6-15 6-17 6-17 6-18 6-18 6-18 6-23 6-24 6-25 6-26 6-33 6-34 A-2 A-3 A-4 A-10
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A.5 A.6 A.7
Serial Device Port Address Selection A-13 Connecting the L80227 to a High-Capacitance Crystal A-14 Connecting the L80227 to a Non High-Capacitance Crystal A-14
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Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Tables 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 4.1 5.1 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 A.1 A.2 A.3 Device Differences Transmit Preamble and SFD Bits at MAC Nibble Interface Receive Preamble and SFD Bits at MAC Nibble Interface 4B/5B Symbol Mapping TP Output Voltage (10 Mbits/s) PLEDn_[1:0] Output Select Bit Encoding LED Normal Function Denition LED Event Denition MI Register Bit Type Denition MI Serial Port Register Summary Absolute Maximum Ratings DC Characteristics Twisted Pair Characteristics (Transmit) Twisted Pair Characteristics (Receive) Test Conditions 25 MHz Input/Output Clock Transmit Timing Receive Timing Collision and Jam Timing Link Pulse Timing Jabber Timing MI Serial Port Timing L80227 Pin List (by Signal Category) L80227 Pin List (by Pin Number) TP Transformer Specication TP Transformer Sources Non High-Capacitance Crystal Specications 2-2 2-6 2-7 2-10 2-17 2-29 2-29 2-30 4-2 5-6 6-1 6-2 6-4 6-5 6-6 6-7 6-8 6-11 6-16 6-19 6-25 6-26 6-27 6-30 A-5 A-5 A-15
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Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 1 Introduction
This chapter contains a brief introduction to the L80227 10BASET/100BASE-TX Ethernet Physical Layer Device (PHY). It contains the following sections: Section 1.1, "Overview" Section 1.2, "Features"
1.1 Overview
This manual describes the L80227 device. The device contains a single PHY channel. The convention used in this manual is that device refers to the IC, and channel refers to the PHY in the device. The L80227 is a highly-integrated analog interface IC for twisted-pair Ethernet applications and can be congured for either 100 Mbits/s (100BASE-TX) or 10 Mbits/s (10BASE-T) Ethernet operation. The PHY channel contains the following blocks: 4B5B Encoder/Manchester Encoder Scrambler 10BASE-T Transmitter 100BASE-TX Transmitter 10BASE-T Receiver 100BASE-TX Receiver Squelch Clock and Data Recovery Link Integrity and Autonegotiation
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
1-1
Descrambler 4B5B Decoder/Manchester Decoder MII Controller Interface Management Interface (MI) Collision Detection Figure 1.1 is a simplied top-level block diagram of the L80227 device. Figure 1.1 Top Level Block Diagram
L80227
OSCIN Oscillator 4B5B Encoder Scrambler 100BASE-TX Transmitter
Manchester Encoder
10BASE-T Transmitter TP Interface
Ethernet Controller
Controller Interface (MII)
Collision Squelch 4B5B Decoder Clock & Data Recovery AutoNegotiation and Link Squelch
Descrambler
100BASE-TX Receiver
Serial Port (MI)
LEDs
LED Drivers
Clock & Data Recovery (Manchester Decoder)
10BASE-T Receiver
Internal output waveshaping circuitry and on-chip lters in the PHY eliminates the need for external lters normally required in 100BASE-TX and 10BASE-T applications.
1-2
Introduction
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Using the on-chip AutoNegotiation algorithm, the device can automatically congure the PHY channel to independently operate in 100 Mbits/s or 10 Mbits/s operation in either full- or half-duplex mode. The device uses the Management Interface (MI) serial port to access eight 16-bit registers in the PHY. These registers comply to Clause 22 of IEEE 802.3u and contain bits and elds that reect conguration inputs, status outputs, and device capabilities. The device is ideally suited as a media interface for 10BASE-T/100BASE-TX repeaters, routers, PCMCIA cards, NIC cards, networked modems, and other end station applications. The device is implemented in either 0.35 or 0.30 micron CMOS technology and operates on a 3.3 V power supply.
1.2 Features
The following list summarizes the salient features of the devices: Single-chip solution for a 10BASE-T/100BASE-TX PHY Dual speed: 10/100 Mbit/s Half-duplex or full-duplex operation MII interface to Ethernet MAC Management Interface (MI) for conguration and status AutoNegotiation for 10/100 Mbit/s, full/half duplex operation AutoNegotiation Advertisement control through pins All applicable IEEE 802.3, 10BASE-T and 100BASE-TX specications are met On-chip wave shaping (no external lters required) Adaptive equalizer for 100BASE-TX operation Baseline wander correction Minimum number of external components LEDs are individually programmable to reect any the following events: - Link
Features
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1-3
- - - -
Activity Collision Full-Duplex 10/100 Mbits/s
3.3 V power supply, 5 V tolerant I/O 64-pin LQFP Operating temperature ranges available: - - Commercial (L80227): 0 to +70 C Industrial (L80227 I): -40 to +85 C
1-4
Introduction
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 2 Functional Description
This chapter contains a functional description of the PHY device. It has the following sections: Section 2.1, "Device Differences" Section 2.2, "Overview" Section 2.3, "Block Diagram Description" Section 2.4, "Start of Packet" Section 2.5, "End of Packet" Section 2.6, "Full-/Half-Duplex Mode" Section 2.7, "10/100 Mbits/s Selection" Section 2.8, "Jabber" Section 2.9, "Reset" Section 2.10, "Receive Polarity Correction"
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-1
2.1 Device Differences
This manual describes the L80227 PHY. It is similar to the L80223 and L80225 PHY devices. Each of these devices is similar with respect to Ethernet operation. Table 2.1 shows the similarities and differences in the devices. Table 2.1
Function Power Supply RESET Pin FX Interface Transmit Transformer Winding Ratio Speed Pin Duplex Pin Hardware Advertisement Control Registers 16 - 20 Available in industrial temperature range
Device Differences
L80223 3.3V Yes Yes 1:1 Yes Yes No Yes No L80225 3.3V Yes No 1:1 Yes Yes Yes #18 No L80227 3.3V Yes No 1:1 Yes Yes No #17, #18 Yes
2-2
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2.2 Overview
This section gives a brief overview of the device functional operation. The L80227 is a complete 100/10 Mbits/s Ethernet Media Interface IC. A block diagram is shown in Figure 2.1. Note: Unless otherwise noted, the operation and specications for the industrial temperature devices are identical to the commercial temperature range device.
2.2.1 Channel Operation
The PHY operates in the 100BASE-TX mode at 100 Mbits/s mode, or in the 10BASE-T mode at 10 Mbits/s. The 100 Mbits/s mode and the 10 Mbits/s mode differ in data rate, signaling protocol, and allowed wiring as follows: 100BASE-TX mode uses two pairs of category 5 or better UTP or STP twisted-pair cable with 4B5B encoded, scrambled, and MLT3 coded 62.5 MHz ternary data to achieve a throughput of 100 Mbits/s. 10 Mbits/s mode uses two pairs of category 3 or better UTP or STP twisted-pair cable with Manchester encoded 10 MHz binary data to achieve a 10 Mbits/s throughput The data symbol format on the twisted-pair cable for the 100 and 10 Mbits/s modes is dened in IEEE 802.3 specications and shown in Figure 2.2.
2.2.2 Data Paths
In each device, there is a transmit data path and a receive data path associated with each PHY channel. The transmit data path is from the Controller Interface to the twisted-pair transmitter. The receive data path is from the twisted-pair receiver to the Controller Interface.
Overview
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-3
Figure 2.1
2-4
L80227 Device Block Diagram
Functional Description
Rev. B Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 2.2
100BASE-TX and 10BASE-T Frame Format
Ethernet MAC Frame
Interframe Gap
PREAMBLE
SFD
DA
SA
LN
LLC Data
FCS
Interframe Gap
100 Base-TX Data Symbols IDLE SSD PREAMBLE SFD DA SA LN LLC DATA FCS ESD IDLE
IDLE = [ 1 1 1 1 ...] SSD = [ 1 1 0 0 0 1 0 0 0 1 ] PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long SFD = [ 1 1 ] DA, SA, LN, LLC DATA, FCS = [ DATA ] ESD = [ 0 1 1 0 1 0 0 1 1 1 ] 10 Base-T Data Symbols IDLE PREAMBLE SFD DA SA LN
Before/After 4B5B Encoding, Scrambling, and MLT3 Coding
LLC DATA
FCS
SOI
IDLE
IDLE = [ NoTransitions ] PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long SFD = [ 1 1 ] DA, SA, LN, LLC DATA, FCS = [ DATA ] SOI = [ 1 1 ] With No MID Bit Transition Before/After Manchester Encoding
Overview
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-5
2.2.2.1 100BASE-TX Operation In 100BASE-TX transmit operation, data is received on the Controller Interface from an external Ethernet controller according to the format shown in Figure 2.3 and Table 2.2. The data is sent to the 4B5B encoder, which scrambles the encoded data. The scrambled data is then sent to the TP transmitter. The TP transmitter converts the encoded and scrambled data into MLT3 ternary format, preshapes the output, and drives the twisted-pair cable. Figure 2.3
TX_EN = 0 IDLE PREAMBLE PRMBLE 62 Bits Start of Frame SFD 2 Bits PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long SFD = [ 1 1 ] DATAn = [Between 64 1518 Data Bytes] IDLE = TX_EN = 0 b. MII Nibble Order First Bit LSB First Nibble MII Nibble Stream TXD0/RXD0 TXD1/RXD1 TXD2/RXD2 TXD3/RXD3 D0 D1 MAC Serial Bit Stream D2 D3 D4 D5 D6 D7 MSB Second Nibble DATA 1
MII Frame Format
a. MII Frame Format TX_EN = 1 DATA Nibbles DATA 2 DATA N-1 DATA N TX_EN = 0 IDLE
Table 2.2
Signals TXDO TXD1 TXD2 TXD3 TX_EN X X X X 0
Transmit Preamble and SFD Bits at MAC Nibble Interface
Bit Value X X X X 0 11 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 12 0 1 0 1 1 0 1 1 1 D03 D44 D1 D2 D3 1 D5 D6 D7 1
1. 2. 3. 4.
1st preamble nibble transmitted. 1st SFD nibble transmitted. 1st data nibble transmitted. D0 through D7 are the rst 8 bits of the data eld.
2-6
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
In 100BASE-TX receive operation, the TP receiver takes incoming encoded and scrambled MLT3 data from the twisted-pair cable, removes any high-frequency noise from the input, equalizes the input signal to compensate for the effects of the cable, performs baseline wander correction, qualies the data with a squelch algorithm, and converts the data from MLT3-encoded levels to internal digital levels. The output of the receiver then goes to a clock and data recovery block that recovers a clock from the incoming data, uses the clock to latch valid data into the device, and converts the data back to NRZ format. The 4B5B decoder and descrambler then decodes and descrambles the NRZ data, respectively, and sends it out of the Controller Interface to an external Ethernet controller. The format of the received data at the Controller interface is as shown in Table 2.3. Table 2.3
Signals RXDO RXD1 RXD2 RXD3 RX_DV X X X X 0 11 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1
Receive Preamble and SFD Bits at MAC Nibble Interface
Bit Value 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 12 0 1 0 1 1 0 1 1 1 D03 D44 D1 D2 D3 1 D5 D6 D7 1
1. First preamble nibble received. Depending on the mode, the device may eliminate either all or some of the preamble nibbles, up to the rst SFD nibble. 2. First SFD nibble received. 3. First data nibble received. 4. D0 through D7 are the rst 8 bits of the data eld.
2.2.2.2 10BASE-T Operation 10BASE-T operation is similar to the 100BASE-TX operation except there is no scrambler/descrambler the encoder/decoder is Manchester instead of 4B5B the data rate is 10 Mbits/s instead of 100 Mbits/s, the twisted-pair symbol data is two-level Manchester instead of ternary MLT-3. the transmitter generates link pulses during the idle period the transmitter detects the jabber condition the receiver detects link pulses and implements the AutoNegotiation algorithm
Overview
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2-7
2.3 Block Diagram Description
The L80227 PHY device has the following main blocks: Oscillator and Clock Controller Interface 4B5B/Manchester Encoder/Decoder Scrambler/Descrambler Twisted-Pair Transmitter Twisted-Pair Receiver Clock and Data Recovery Link Integrity/AutoNegotiation Descrambler Link Indication Collision Detection LED Drivers A Management Interface (MI) serial port provides access to eight internal PHY registers. Figure 2.1 shows the main blocks, along with their associated signals. The following sections describe each of the blocks in Figure 2.1. The performance of the device in both the 10 and 100 Mbits/s modes is described.
2.3.1 Oscillator and Clock
The L80227 requires a 25 MHz reference frequency for internal signal generation. This 25 MHz reference frequency is generated with either an external 25 MHz crystal connected between OSCIN and GND or with the application of an external 25 MHz clock to OSCIN. The device provides either a 2.5 MHz or 25 MHz reference clock at the TX_CLK or RX_CLK output pins for 10-MHz or 100 MHz operation, respectively.
2-8
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2.3.2 Controller Interface
This section describes the controller interface operation. 2.3.2.1 High Impedance Control When the RX_EN pin is LOW, the following controller interface outputs are placed in the high impedance state: RX_CLK RXD[3:0] RX_DV RX_ER COL 2.3.2.2 MII Interface The device has an MII interface to an external Ethernet Media Access Controller (MAC). MII (100 Mbits/s) - The MII is a nibble-wide packet data interface dened in IEEE 802.3 and shown in Figure 2.3. The L80227 meets all the MII requirements outlined in IEEE 802.3. The L80227 can directly connect, without any external logic, to any Ethernet controller or other device that also complies with the IEEE 802.3 MII specications. The MII interface contains the following signals: Transmit data bits (TXD[3:0]) Transmit clock (TX_CLK) Transmit enable (TX_EN) Transmit error (TX_ER) Receive data bits (RXD[3:0]) Receive clock (RX_CLK) Carrier sense (CRS) Receive data valid (RX_DV) Receive data error (RX_ER) Collision (COL).
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-9
The transmit and receive clocks operate at 25 MHz in 100 Mbits/s mode. On the transmit side, the TX_CLK output runs continuously at 25 MHz. When no data is to be transmitted, TX_EN must be deasserted. While TX_EN is deasserted, TX_ER and TXD[3:0] are ignored and no data is clocked into the device. When TX_EN is asserted on the rising edge of TX_CLK, data on TXD[3:0] is clocked into the device on the rising edge of the TX_CLK output clock. TXD[3:0] input data is nibble-wide packet data whose format must be the same as specied in IEEE 802.3 and shown in Figure 2.3. When all data on TXD[3:0] has been latched into the device, TX_EN must be deasserted on the rising edge of TX_CLK. TX_ER is also clocked in on the rising edge of TX_CLK. TX_ER is a transmit error signal. When this signal is asserted, the device substitutes an error nibble in place of the normal data nibble that was clocked in on TXD[3:0]. The error nibble is dened to be the /H/ symbol, which is dened in IEEE 802.3 and shown in Table 2.4. Table 2.4 4B/5B Symbol Mapping
Description Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D 5B Code 0b11110 0b01001 0b10100 0b10101 0b01010 0b01011 0b01110 0b01111 0b10010 0b10011 0b10110 0b10111 0b11010 0b11011 4B Code 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101
Symbol Name 0 1 2 3 4 5 6 7 8 9 A B C D
2-10
Functional Description
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Table 2.4
4B/5B Symbol Mapping (Cont.)
Description Data E Data F Idle SSD #1 SSD #2 ESD #1 ESD #2 Halt Invalid codes 5B Code 0b11100 0b11101 0b11111 0b11000 0b10001 0b01101 0b00111 0b00100 All others1 4B Code 0b1110 0b1111 0b0000 0b0101 0b0101 0b0000 0b0000 Undened 0b0000*
Symbol Name E F I J K T R H -
1. These 5B codes are not used. The decoder decodes these 5B codes to 4B 0000. The encoder encodes 4B 0000 to 5B 11110, as shown in symbol Data 0.
Because the OSCIN input clock generates the TX_CLK output clock, the TXD[3:0], TX_EN, and TX_ER signals are also clocked in on rising edges of OSCIN. On the receive side, as long as a valid data packet is not detected, CRS and RX_DV are deasserted and the RXD[3:0] signals are held LOW. When the start of packet is detected, CRS and RX_DV are asserted on the falling edge of RX_CLK. The assertion of RX_DV indicates that valid data is clocked out on RXD[3:0] on the falling edge of the RX_CLK. The RXD[3:0] data has the same frame structure as the TXD[3:0] data and is specied in IEEE 802.3 and shown in Figure 2.3. When the end of the packet is detected, CRS and RX_DV are deasserted, and RXD[3:0] is held LOW. CRS and RX_DV also stay deasserted if the device is in the Link Fail State. RX_ER is a receive error output that is asserted when certain errors are detected on a data nibble. RX_ER is asserted on the falling edge of RX_CLK for the duration of that RX_CLK clock cycle during which the nibble containing the error is output on RXD[3:0]. The collision output, COL, is asserted whenever the collision condition is detected.
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-11
MII (10 Mbits/s) - MII 10 Mbits/s operation is identical to 100 Mbits/s operation except TX_CLK and RX_CLK clock frequency is reduced to 2.5 MHz TX_ER is ignored RX_ER is disabled and always held LOW Receive operation is modied as follows: On the receive side, when the squelch circuit determines that invalid data is present on the TP inputs, the receiver is idle. During idle, RX_CLK follows TX_CLK, RXD[3:0] is held LOW, and CRS and RX_DV are deasserted. When a start of packet is detected on the TP receive inputs, CRS is asserted and the clock recovery process starts on the incoming TP input data. After the receive clock is recovered from the data, the RX_CLK is switched over to the recovered clock and the data valid signal RX_DV is asserted on a falling edge of RX_CLK. Once RX_DV is asserted, valid data is clocked out on RXD[3:0] on the falling edge of RX_CLK. The RXD[3:0] data has the same packet structure as the TXD[3:0] data and is formatted on RXD[3:0] as specied in IEEE 802.3 and shown in Figure 2.3. When the end of packet is detected, CRS and RX_DV are deasserted. CRS and RX_DV also stay deasserted as long as the device is in the Link Fail State. MII Disable - To disable the MII inputs and outputs, set the MII_DIS bit in the MI serial port Control register. When the MII is disabled, the MII inputs are ignored, and the MII and TP outputs are placed in a highimpedance state. If the MI address lines, MDA[3:0]n, are pulled HIGH during reset or powerup, the L80227 powers up and resets with the MII disabled. Otherwise, the L80227 powers up and resets with the MII enabled.
2.3.3 Encoder
This section describes the 4B5B encoder, which is used in 100 Mbits/s operation. It also describes the Manchester Encoder, used in 10BASE-T operation.
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2.3.3.1 4B5B Encoder (100 Mbits/s) 100BASE-TX operation requires that the data be 4B5B encoded. The 4B5B Encoder block shown in Figure 2.1 converts the four-bit data nibbles into ve-bit data words. The mapping of the 4B nibbles to 5B codewords is specied in IEEE 802.3 and is shown in Table 2.4. The 4B5B encoder takes 4B (four-bit) nibbles from the Transmit MAC block, converts them into 5B (ve-bit) words according to Table 2.4, and sends the 5B words to the scrambler. The 4B5B encoder also substitutes the rst eight bits of the preamble with the Start of Stream Delimiter (SSD) (/J/K/ symbols) and adds an End of Stream Delimiter (ESD) (/T/R/ symbols) to the end of each packet, as dened in IEEE 802.3 and shown in Figure 2.2. The 4B5B encoder also lls the period between packets (idle period), with a continuous stream of idle symbols, as shown in Figure 2.2. 2.3.3.2 Manchester Encoder (10 Mbits/s) The Manchester Encoder shown in Figure 2.1 is used for 10 Mbits/s operation. It combines clock and non-return to zero inverted (NRZI) data such that the rst half of the data bit contains the complement of the data, and the second half of the data bit contains the true data, as specied in IEEE 802.3. This process guarantees that a transition always occurs in the middle of the bit cell. The Manchester encoder on the device converts the 10 Mbits/s NRZI data from the Ethernet controller interface into a single data stream for the TP transmitter and adds a start of idle pulse (SOI) at the end of the packet as specied in IEEE 802.3 and shown in Figure 2.2. The Manchester encoding process is only done on actual packet data; during the idle period between packets, no signal is transmitted except for periodic link pulses.
2.3.4 Decoder
This section describes the 4B5B decoder, used in 100 Mbits/s operation, which converts 5B encoded data to 4B nibbles. It also describes the Manchester Decoder, used in 10BASE-T operation. 2.3.4.1 4B5B Decoder (100 Mbits/s) Because the TP input data is 4B5B encoded on the transmit side, the 4B5B decoder must decode it on the receive side. The mapping of the
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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5B codewords to the 4B nibbles is specied in IEEE 802.3. The 4B5B decoder takes the 5B codewords from the descrambler, converts them into 4B nibbles according to Table 2.4, and sends the 4B nibbles to the receive Ethernet controller. The 4B5B decoder also strips off the SSD delimiter (/J/K/ symbols), and replaces it with two 4B Data 5 nibbles (/5/ symbol). It also strips off the ESD delimiter (/T/R/ symbols), and replaces it with two 4B Data 0 nibbles (/I/ symbol), per IEEE 802.3 specications (see Figure 2.2). The 4B5B decoder detects SSD, ESD, and codeword errors in the incoming data stream as specied in IEEE 802.3. To indicate these errors, the device asserts the RX_ER output while the errors are being transmitted across RXD[3:0]. 2.3.4.2 Manchester Decoder (10 Mbits/s) In Manchester coded data, the rst half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. The Manchester Decoder converts the single data stream from the TP receiver into non-return to zero (NRZ) data for the controller interface. To do this, it decodes the data and strips off the SOI pulse. Because the Clock and Data Recovery block has already separated the clock and data from the TP receiver, that block inherently performs the the Manchester decoding.
2.3.5 Scrambler
100BASE-TX transmission requires scrambling to reduce the radiated emissions on the twisted pair. The scrambler takes the NRZI encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specications, and sends it to the TP transmitter. A scrambler is not used for 10 Mbits/s operation.
2.3.6 Descrambler
The descrambler block shown in Figure 2.1 is used in 100BASE-TX operation. The device descrambler takes the scrambled NRZI data from the data recovery block, descrambles it according to IEEE 802.3 specications, aligns the data on the correct 5B word boundaries, and sends it to the 4B5B decoder.
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
The algorithm for synchronization of the descrambler is the same as the algorithm outlined in the IEEE 802.3 specication. After the descrambler is synchronized, it maintains synchronization as long as enough descrambled idle pattern ones are detected within a given interval. To stay in synchronization, the descrambler needs to detect at least 25 consecutive descrambled idle pattern ones in a 1 ms interval. If 25 consecutive descrambled idle pattern ones are not detected within the 1 ms interval, the descrambler goes out of synchronization and restarts the synchronization process. The descrambler is disabled for 10BASE-T operation.
2.3.7 Twisted-Pair Transmitters
This section describes the operation of the 10 and 100 Mbits/s TP transmitters. 2.3.7.1 100 Mbits/s TP Transmitter The TP transmitter consists of an MLT3 encoder, waveform generator, and line driver. The MLT3 encoder converts the NRZI data from the scrambler into a three-level code required by IEEE 802.3. MLT3 coding uses three levels, converting ones to transitions between the three levels, and zeros to no transitions or changes in level. The purpose of the waveform generator is to shape the transmit output pulse. The waveform generator takes the MLT3 three-level encoded waveform and uses an array of switched current sources to control the shape of the twisted-pair output signal. The waveform generator consists of switched current sources, a clock generator, lter, and logic. The switched current sources control the rise and fall time as well as signal level to meet IEEE 802.3 requirements. The output of the switched current sources goes through a second order low-pass lter that "smooths" the current output and removes any high-frequency components. In this way, the waveform generator preshapes the output waveform transmitted onto the twisted-pair cable such that the waveform meets the pulse template requirements outlined in IEEE 802.3. The waveform generator eliminates the need for any external lters on the TP transmit output.
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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The line driver converts the shaped and smoothed waveform to a current output that can drive greater than 100 meters of category 5 unshielded twisted-pair cable or 150-ohm shielded twisted-pair cable. 2.3.7.2 10 Mbits/s TP Transmitter Even though the 10 Mbits/s transmitter operation is much different than that of 100 Mbits/s, it also consists of a waveform generator and line driver (see Figure 2.1). The waveform generator, which consists of a ROM, DAC, clock generator, and lter, shapes the output transmit pulse. The DAC generates a stair-stepped representation of the desired output waveform. The stair-stepped DAC output then is passed through a low-pass lter to "smooth" the DAC output and remove any high-frequency components. The DAC values are determined from the data at the ROM addresses. The data is chosen to shape the pulse to the desired template. The clock generator clocks the data into the DAC at high speed. In this way, the waveform generator preshapes the output waveform to be transmitted onto the twisted-pair cable to meet the pulse template requirements outlined in IEEE 802.3 Clause 14 and shown in Figure 2.4. The waveshaper replaces and eliminates external lters on the TP transmit output. The line driver converts the shaped and smoothed waveform to a current output that can drive greater than 100 meters of category 3/4/5 100-ohm unshielded twisted-pair cable or 150-ohm shielded twisted-pair cable without any external lters. During the idle period, no output signals are transmitted on the TP outputs except for link pulses.
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 2.4
Voltage (V) 1.0 0.8 0.6 0.4 0.2 0.0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 0 A
TP Output Voltage Template
B N
P H D C E Q F M J R S LK W U V I O
G 10
T
T 60 70 80 90 100 110
20
30
40
50
Time (ns)
Table 2.5
TP Output Voltage (10 Mbits/s)
Time (ns) Internal MAU 0 15 15 25 32 42 57 48 67 92 74 73 Voltage (V) 0 1.0 0.4 0.55 0.45 0 1.0 0.7 0.6 0 0.55 0.55
Reference A B C D E F G H I J K L
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-17
Table 2.5
TP Output Voltage (10 Mbits/s) (Cont.)
Time (ns) Internal MAU 58 85 100 110 111 108 111 110 100 110 90 Voltage (V) 0 1.0 0.4 0.75 0.15 0 0.15 1.0 0.3 0.7 0.7
Reference M N O P Q R S T U V W
2.3.8 Twisted-Pair Receiver
The device is capable of operating at either 10- or 100-Mbits/s. This section describes the twisted-pair receivers and squelch operation for both modes of operation. 2.3.8.1 100 Mbits/s TP Receiver The TP receiver detects input signals from the twisted-pair input and converts them to a digital data bit stream ready for clock and data recovery. The receiver can reliably detect 100BASE-TX compliant transmitter data that has been passed through 0 to 100 meters of 100-ohm category 5 UTP or 150-ohm STP cable. The 100 Mbits/s receiver consists of an adaptive equalizer, baseline wander correction circuit, comparators, and an MLT3 decoder. The TP inputs rst go to an adaptive equalizer. The adaptive equalizer compensates for the low-pass characteristics of the cable and can adapt and compensate for 0 to 100 meters of category 5, 100-ohm or 150-ohm STP cable. The baseline wander correction circuit restores the DC component of the input waveform that the external transformers have removed. The comparators convert the equalized signal back to digital levels and qualify the data with the squelch circuit. The MLT3 decoder
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
takes the three-level MLT3 encoded output data from the comparators and converts it to normal digital data to be used for clock and data recovery. 2.3.8.2 10 Mbits/s TP Receiver The 10 Mbits/s receiver detects input signals from the twisted-pair cable that are within the template shown in Figure 2.5. The TP inputs are biased by internal resistors and go through a low-pass lter designed to eliminate any high-frequency input noise. The output of the receive lter goes to two different types of comparators: squelch and zero crossing. The squelch comparator determines whether the signal is valid, and the zero-crossing comparator senses the actual data transitions after the signal is determined to be valid. The output of the squelch comparator goes to the squelch circuit and is also used for link pulse detection, SOI detection, and reverse polarity detection. The output of the zero-crossing comparator is used for clock and data recovery in the Manchester decoder. Figure 2.5 TP Input Voltage Template (10 Mbits/s)
Short Bit 3.1 V
Slope 0.5 V/ns
585 mV 585 mV sin ( 0 Long Bit t/PW) PW 3.1 V Slope 0.5 V/ns 585 mV 585 mV sin ( 585 mV sin[2 0 PW/4 t/PW) (t PW2)/PW)] 3PW/4 PW
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-19
2.3.8.3 Squelch (100 Mbits/s) The Squelch block determines if the TP input contains valid data. The 100 Mbits/s TP squelch is one of the criteria used to determine link integrity. The squelch comparators compare the TP inputs against xed positive and negative thresholds called squelch levels. The output from the squelch comparator goes to a digital squelch circuit, which determines whether the receive input data on that port is valid. If the data is invalid, the receiver is in the squelched state. If the input voltage exceeds the squelch levels at least four times with alternating polarity within a 10 s interval, the squelch circuit determines that the data is valid and the receiver enters into the unsquelch state. In the unsquelch state, the receive threshold level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level. When the receiver is in the unsquelch state, the input signal is considered valid. The device stays in the unsquelch state until loss of data is detected. Loss of data is detected if no alternating polarity unsquelch transitions are detected during any 10 s interval. When a loss of data is detected, the receive squelch is turned on again. 2.3.8.4 Squelch (10 Mbits/s) The TP squelch algorithm for 10 Mbits/s mode is identical to the 100 Mbits/s mode, except the 10 Mbits/s TP squelch algorithm is not used for link integrity, but to sense the beginning of a packet the receiver goes into the unsquelch state if the input voltage exceeds the squelch levels for three bit times with alternating polarity within a 50 to 250 ns interval the receiver goes into the squelch state when SOI is detected unsquelch detection has no effect on link integrity (link pulses are used in 10 Mbits/s mode for that purpose) start of packet is determined when the receiver goes into the unsquelch state and CRS is asserted the receiver meets the squelch requirements dened in IEEE 802.3 Clause 14.
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2.3.9 Clock and Data Recovery
This section describes clock and data recovery methods implemented in the device for both the 100 Mbits/s and 10 Mbits/s modes. 2.3.9.1 100 Mbits/s Clock and Data Recovery Clock recovery is accomplished with a phase-locked-loop (PLL). If valid data is not present on the receive inputs, the PLL is locked to the 25 MHz TX_CLK signal. When the squelch circuit detects valid data on the receive TP input, and if the device is in the Link Pass state, the PLL input is switched to the incoming data on the receive inputs. The PLL then locks on to the transitions in the incoming signal to recover the clock. The recovered data clock is then used to generate the 25 MHz RX_CLK, which clocks data into the controller interface section. The recovered clock extracted by the PLL latches in data from the TP receiver to perform data recovery. The data is then converted from a single bit stream into nibble-wide data words according to the format shown in Figure 2.3 2.3.9.2 10 Mbits/s Clock and Data Recovery The clock recovery process for 10 Mbits/s mode is identical to the 100 Mbits/s mode except the recovered clock frequency is a 2.5 MHz nibble clock the PLL is switched from TX_CLK to the TP input when the squelch indicates valid data the PLL takes up to 12 transitions (bit times) to lock onto the preamble, so some of the preamble data symbols are lost. However, the clock recovery block recovers enough preamble symbols to pass at least six nibbles of preamble to the receive controller interface as shown in Figure 2.3. The data recovery process for 10 Mbits/s mode is identical to that of the 100 Mbits/s mode. As mentioned in the Manchester Decoder section, the data recovery process inherently performs decoding of Manchester encoded data from the TP inputs.
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-21
2.3.10 Link Integrity and AutoNegotiation
The device can be congured to implement either the standard link integrity algorithms or the AutoNegotiation algorithm. The standard link integrity algorithms are used solely to establish a link to and from a remote device. The AutoNegotiation algorithm is used to establish a link to and from a remote device and automatically congure the device for 10 or 100 Mbits/s and Half- or Full-Duplex operation. The different standard link integrity algorithms for 10 and 100 Mbits/s modes are described in following subsections. The AutoNegotiation algorithm in the device meets all requirements specied in IEEE 802.3. 2.3.10.1 10BASE-T Link Integrity Algorithm (10 Mbits/s) The device implements the same 10BASE-T link integrity algorithm that is dened in IEEE 802.3. This algorithm uses normal link pulses (NLPs), which are transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called Link Pass state). The transmit link pulse meets the template requirements dened in IEEE 802.3 and shown in Figure 2.6. Refer to IEEE 802.3 for more details if needed.
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 2.6
Link Pulse Output Voltage Template (10 Mbits/s)
0 BT 1.3 BT
3.1 V 0.5 V/ns 585 mV 0.5 BT 0.6 BT 2.0 BT 300 mV 4.0 BT
+ 50 mV 50 mV 0.25 BT
+ 50 mV 50 mV
200 mV 4.0 BT 42.0 BT
3.1 V 0.85 BT 2.0 BT
2.3.10.2 100BASE-TX Link Integrity Algorithm (100 Mbits/s) Because the IEEE 802.3 specication denes 100BASE-TX to have an active idle signal, the device uses the squelch criteria and descrambler synchronization algorithm on the input data to determine if the device has successfully established a link with a remote device (called Link Pass state). Refer to IEEE 802.3 for more details if needed. 2.3.10.3 AutoNegotiation Algorithm As stated previously, the AutoNegotiation algorithm is used for two purposes: to establish a link to and from a remote device to automatically congure the device for either 10 or 100 Mbits/s operation and either Half- or Full-Duplex operation. The AutoNegotiation algorithm is the same algorithm dened in IEEE 802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called fast link pulses (FLPs), to pass up to 16 bits of signaling data back and forth between the device and a remote device. The transmit FLP pulses meet
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-23
the template specied in IEEE 802.3 and shown in Figure 2.6. A timing diagram contrasting NLPs and FLPs is shown in Figure 2.7. Figure 2.7 NLP vs FLP Link Pulse
Normal Link Pulse (NLP) TX_DI Fast Link Pulse (FLP) TX_DI D0 D1 D2 D3 D14 D15
Clock Clock Clock Clock Clock Clock Clock Data Data Data Data Data Data
To enable AutoNegotiation for a channel, assert the AutoNegotiation pin (ANEG), or set the AutoNegotiation Enable (ANEG_EN) bit in the MI serial port Control register (register 0). If AutoNegotiation is enabled, any of the following events initiates the AutoNegotiation algorithm for the channel: Power up Device reset Channel enters the Link Fail state AutoNegotiation Enable (ANEG_EN) bit in the MI serial port Control register for that port is cleared, then set AutoNegotiation Reset (ANEG_RST) bit in the MI serial port Control register is set Once a negotiation has been initiated, the device rst determines if the remote device has AutoNegotiation capability. If the remote device is not AutoNegotiation-capable and is just transmitting either 10BASE-T or 100BASE-TX signals, the device senses it and places itself in the same mode as the remote device. If the device detects FLPs from the remote device, the remote device is determined to have AutoNegotiation capability, and the device then uses the value from the PHY AutoNegotiation Advertisement for that port to advertise its capabilities to
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
the remote device. The device negotiation algorithm matches its capabilities to the remote device's capabilities and determines what mode the device should be congured for according to the priority resolution algorithm dened in IEEEE 802.3 Clause 28. After the negotiation process is completed, the device congures itself for either 10 or 100 Mbits/s modes and either Half- or Full-Duplex modes (depending on the outcome of the negotiation process), and switches to either the 10BASE-T or 100BASE-TX link integrity algorithms (depending on which mode AutoNegotiation enabled). Refer to IEEE 802.3 Clause 28 for more details. 2.3.10.4 AutoNegotiation Outcome Indication The outcome or result of the AutoNegotiation process is stored in the 10/100 Speed Detect (SPD_DET) and Duplex Detect (DPLX_DET) bits in the MI serial port Status Output 0 register. 2.3.10.5 AutoNegotiation Status To monitor the status of the AutoNegotiation process, read the AutoNegotiation Acknowledgement (ANEG_ACK) bit in the MI serial port Status register. 2.3.10.6 AutoNegotiation Enable/Disable To enable the AutoNegotiation algorithm, set the AutoNegotiation Enable bit (ANEG_EN) in the MI serial port Control register, or assert the ANEG pin. To disable the AutoNegotiation algorithm, clear the ANEG_EN bit or deassert the ANEG pin. When the AutoNegotiation algorithm is enabled, the device halts all transmissions including link pulses for 1200 to 1500 ms, enters the Link Fail State, and restarts the negotiation process. When the AutoNegotiation algorithm is disabled, the selection of 100 Mbits/s or 10 Mbits/s mode is determined with the state of the SPEED bit in the MI serial port Control register and the half- or full-duplex mode is determined with the state of the DPLX bit in the MI serial port Control register.
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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2.3.10.7 AutoNegotiation Reset Appropriately setting the AutoNegotiation Reset (ANEG_RST) bit in the MI serial port Control register can initiate or reset the AutoNegotiation algorithm at any time.
2.3.11 Link Indication
Receive link detect activity can be monitored two ways: 1. The link detect bit (LINK) in the MI serial port Status register indicates link activity when it is set. 2. The LED output pins can be programmed to indicate link activity. In the MI serial port Conguration register, set the LED function select bits (LED_DEF_[1:0]) so that link activity is indicated at the PLED3n or PLED0n output. Set the PLED3_[1:0] and PLED0_[1:0] bits in the same register to 0b11 (normal). With these settings, LEDs connected to the PLED3n and PLED0n pins will reect link activity. When either the PLED3n or PLED0n pins are programmed to be a link detect output, they are driven LOW whenever the device is in the Link Pass State. The PLED3n output is open-drain with a pullup resistor and can drive an LED from VDD. The PLED0n output has both pullup and pulldown driver transistors in addition to a weak pullup resistor, so it can drive an LED from either VDD or GND. Both the PLED3n and PLED0n outputs can also drive another digital input. See Section 2.3.13, "LED Drivers," page 2-28 for more details on how to program the LED output pins to indicate various conditions.
2.3.12 Collision
Collisions occur whenever transmit and receive operations occur simultaneously while the device is in Half-Duplex mode. 2.3.12.1 100 Mbits/s In 100 Mbits/s operation, a collision occurs and is sensed whenever there is simultaneous transmission (packet transmission on TPO+/-) and reception (non-idle symbols detected at the TP+/- input). When a
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
collision is detected, the COL output is asserted, TP data continues to be transmitted on the twisted-pair outputs, TP data continues to be received on the twisted-pair inputs, and internal CRS loopback is disabled. After a collision is in process, CRS is asserted and stays asserted until the receive and transmit packets that caused the collision are terminated. The collision function is disabled if the device is in the Full-Duplex mode, is in the Link Fail state, or if the device is in the diagnostic loopback mode. 2.3.12.2 10 Mbits/s A collision in the 10 Mbits/s mode is identical to one the 100 Mbits/s mode except the 10 Mbits/s squelch criteria determines reception the RXD[3:0] outputs are forced to all zeros the collision signal (COL) is asserted when the SQE test is performed the collision signal (COL) is asserted when the jabber condition has been detected. 2.3.12.3 Collision Test To test the Controller Interface collision signal (COL), set the COLTST bit in the MI serial port Control register. When this bit is set, TX_EN is looped back onto COL and the TP outputs are disabled. 2.3.12.4 Collision Indication Collisions are indicated through the COL pin, which is asserted HIGH every time a collision occurs. The device can also be programmed to indicate collisions on the PLED2n output. In the MI serial port Conguration register, set the LED function select bits (LED_DEF_[1:0]) so that collision activity is indicated at the PLED2n output. Set the PLED2_[1:0] bits in the same register to 0b11 (normal). With these settings, an LED connected to the PLED2n pin will reect collision activity.
Block Diagram Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-27
When the PLED2n pin is programmed to be a collision detect output, it is asserted LOW for 100 ms every time a collision occurs. The PLED2n output is open drain with a pullup resistor and can drive an LED from VDD or can drive another digital input. See Section 2.3.13, "LED Drivers," page 2-28 for more details on how to program the LED output pins to indicate various conditions.
2.3.13 LED Drivers
The PLED[5:2]n outputs are open-drain with a pullup resistor and can drive LEDs tied to VDD. The PLED[1:0]n outputs have both pullup and pulldown driver transistors with a pullup resistor, so the PLED[1:0]n outputs can drive LEDs tied to either VDD or GND. The PLED[5:0]n outputs can be programmed through the MI serial port Conguration register for the following functions: Normal Function On Off Blink The PLED[5:0]n outputs are programmed with the LED output select bits (PLEDn_[1:0]) and the LED Normal Function select bits (LED_DEF[1:0]) in the MI serial port Conguration register. 2.3.13.1 LED Output Select Bits There are four sets of output select bits in MI serial port Conguration register, one set for each LED output pin: PLED3_[1:0] control the PLED3n output PLED2_[1:0] control the PLED2n output PLED1_[1:0] control the PLED1n output PLED0_[1:0] control the PLED0n output The PLEDn_[1:0] bits program the outputs to operate in the following modes:
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Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Normal operation (see Section 2.3.13.2, "LED Normal Function Select Bits") Blink Steady On (PLED[3:0]n pin LOW) Steady Off (PLED[3:0]n pin HIGH) Table 2.6 shows the encoding of the output select bits. Table 2.6
PLEDn_[1] 1 1 0 0
PLEDn_[1:0] Output Select Bit Encoding
PLEDn_[0] 1 0 1 0 LED State Normal LED Blink LED On LED Off LED Pin LED pin reects the functions selected with the LED_DEF[1:0] bits LED output driver continuously toggles at a rate of 100 ms on, 100 ms off LED output driver is LOW LED output driver is HIGH
2.3.13.2 LED Normal Function Select Bits When the PLED[5:0]n pins are programmed for their normal functions (PLEDn_[1:0] = 0b11), the pin output states indicate four specic types of events. The LED Normal Function select bits (LED_DEF[1:0]) in the MI serial port Conguration register determine the states of the pins, as indicated in Table 2.7 and Table 2.8. Table 2.7 LED Normal Function Denition
PLED5n RCV ACT RCV ACT RCV ACT RCV ACT PLED4n XMT ACT XMT ACT XMT ACT XMT ACT PLED3n LINK LINK LINK + ACT LINK 100 PLED2n COL ACT COL ACT PLED1n FDX FDX FDX FDX PLED0n 10/100 10/100 10/100 LINK10
LED_DEF[1:0] 0b11 0b10 0b01 0b001
1. The L80227 powers up with the LED_DEF[1:0] bits set to the default value of 0b00.
Block Diagram Description
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2-29
The default Normal Functions for PLED[5:0]n are Receive Activity, Transmit Activity, Link 100, Activity, Full Duplex, and Link 10, respectively. Table 2.8
Symbol RCV ACT XMT ACT LINK LINK+ACT
LED Event Denition
Denition Receive activity occurred; stretch pulse to 100 ms Transmit activity occurred; stretch pulse to 100 ms 100 or 10 Mbits/s link detected 100 or 10 Mbits/s link detected or activity occurred; stretch pulse to 100 ms (link detect causes LED to be on, activity causes LED to blink) Activity occurred; stretch pulse to 100 ms 100 Mbit/s link detected Collision occurred; stretch pulse to 100 ms Full-Duplex mode enabled 10 Mbits/s mode enabled (HIGH), or 100 Mbits/s mode enabled (LOW) 10 Mbits/s link detected
ACT LINK100 COL FDX 10/100 LINK10
2.4 Start of Packet
This section describes start of packet operation for both the 100 Mbits/s and 10 Mbits/s modes.
2.4.1 100 Mbits/s
A unique Start of Stream Delimiter (SSD) indicates the start of packet for 100 Mbits/s mode. The SSD pattern consists of two /J/K/ 5B symbols inserted at the beginning of the packet in place of the rst two preamble symbols, as dened in IEEE 802.3 Clause 24 and shown in Table 2.4 and Figure 2.2. The 4B5B encoder generates the transmit SSD and inserts the /J/K/ symbols at the beginning of the transmit data packet in place of the rst two 5B symbols of the preamble, as shown in Figure 2.2.
2-30
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
The 4B5B decoder detects the receive pattern. To do this, the decoder examines groups of 10 consecutive code bits (two 5B words) from the descrambler. Between packets, the receiver detects the idle pattern (5B /I/ symbols). When in the idle state, the device deasserts the CRS and RX_DV pins. If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /J/K/ symbols, the start of packet is detected, data reception begins, and /5/5/ symbols are substituted in place of the /J/K/ symbols. If the receiver is in the idle state and 10 consecutive code bits from the receiver are a pattern that is neither /I/I/ nor /J/K/ symbols, but contain at least two noncontiguous zeros, activity is detected but the start of packet is considered to be faulty and a False Carrier Indication (also referred to as bad SSD) is signaled to the controller interface. When False Carrier is detected, CRS is asserted, RX_ER is asserted, RX_DV remains deasserted, and the RXD[3:0] output state is 0b1110 while RX_ER is asserted. If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/I/ nor /J/K/ symbols but does not contain at least two noncontiguous zeros, the data is ignored and the receiver stays in the idle state.
2.4.2 10 Mbits/s
Because the idle period in 10 Mbits/s mode is dened to be when there is no valid data on the TP inputs, the start of packet for 10 Mbits/s mode is detected when the TP squelch circuit detects valid data. When the start of packet is detected, CRS is asserted as described in Section 2.3.2, "Controller Interface," page 2-9. See Section 2.3.8.4, "Squelch (10 Mbits/s)," page 2-20 for details on the squelch algorithm.
2.5 End of Packet
This section describes end of packet operation for both the 100 Mbits/s and 10 Mbits/s modes.
End of Packet
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-31
2.5.1 100 Mbits/s
The End of Stream Delimiter (ESD) indicates the end of packet for 100 Mbits/s mode. The ESD pattern consists of two /T/R/ 4B5B symbols inserted after the end of the packet, as dened in IEEE 802.3 Clause 24 and shown in Table 2.4 and Figure 2.2. The 4B5B encoder generates the transmit ESD and inserts the /T/R/ symbols after the end of the transmit data packet, as shown in Figure 2.2. The 4B5B decoder detects the ESD pattern when there are groups of 10 consecutive code bits (two 5B words) from the descrambler during valid packet reception. If the 10 consecutive code bits from the receiver during valid packet reception consist of the /T/R/ symbols, the end of packet is detected, data reception is terminated, the CRS and RX_DV pins are asserted, and /I/I/ symbols are substituted in place of the /T/R/ symbols. If the 10 consecutive code bits from the receiver during valid packet reception do not consist of /T/R/ symbols, but instead consist of /I/I/ symbols, the packet is considered to have been terminated prematurely and abnormally, and the end of packet condition is signalled to the controller interface. When the premature end of packet condition is detected, the RX_ER signal is asserted for the nibble associated with the rst /I/ symbol detected, then the CRS and RX_DV pins are deasserted.
2.5.2 10 Mbits/s
The end of packet for 10 Mbits/s mode is indicated with the Start of Idle (SOI) pulse. The SOI pulse is a positive double wide pulse containing a Manchester code violation inserted at the end of every packet. The TP transmitter generates the transmit SOI pulse and inserts it at the end of the data packet after TX_EN has been deasserted. The transmit waveshaper shapes the transmitted SOI output pulse at the TP output to meet the pulse template requirements specied in IEEE 802.3 Clause 14 and shown in Figure 2.8.
2-32
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 2.8
SOI Output Voltage Template (10 Mbits/s)
0 BT 4.5 BT
3.1 V 0.5 V/ns
0.25 BT 2.25 BT 585 mV
6.0 BT + 50 mV 50 mV 45.0 BT
585 mV sin (2 (t/1 BT)) 0 t 0.25 BT and 225 t 2.5 BT
3.1 V 2.5 BT 4.5 BT
The TP receiver senses missing data transitions in order to detect the receive SOI pulse. Once the SOI pulse is detected, data reception is ended and the CRS and RX_DV pins are deasserted.
2.6 Full-/Half-Duplex Mode
Half-Duplex mode is the CSMA/CD operation dened in IEEE 802.3. It allows transmission or reception, but not both at the same time. FullDuplex operation is a mode that allows simultaneous transmission and reception. Full duplex in the 10 Mbits/s mode is identical to operation in the 100 Mbits/s mode. The device can be forced into either the Full- or Half-Duplex mode, or the device can use AutoNegotiation to autoselect Full-/Half-Duplex operation. When a channel is placed in Full-Duplex mode: The collision function is disabled, and TX_EN to CRS loopback is disabled
Full-/Half-Duplex Mode
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-33
2.6.1 Forcing Full-/Half-Duplex Operation
To independently force a channel into either the Full- or Half-Duplex mode, set the Duplex Mode Select (DPLX) bit in the MI serial port Control register, assuming that AutoNegotiation is not enabled with the ANEG_EN bit in the MI serial port Control register. The device automatically congures itself for Full- or Half-Duplex mode. To do this, the device uses the AutoNegotiation algorithm to advertise and detect Full- and Half-Duplex capabilities to and from a remote device. To enable AutoNegotiation, set the AutoNegotiation Enable (ANEG_EN) bit in the MI serial port Control register. To select the advertised Full/-Half-Duplex capability, appropriately set the bits in the MI serial port AutoNegotiation Advertisement register. AutoNegotiation functionality is described in more detail in Section 2.3.10, "Link Integrity and AutoNegotiation".
2.6.2 Full/Half Duplex Indication
Full-Duplex detection can be monitored through the DPLX_DET bit in the MI serial port Status Output register, or it can also be programmed to appear on the PLED1n pin. In the MI serial port Conguration register, set the LED function select bits (LED_DEF[1:0]) so that the Full-Duplex condition activity is indicated at the PLED1n output. Set the PLED2_[1:0] bits in the same register to 0b11 (normal). When the PLED1n pin is programmed to be a Full-Duplex detect output, it is asserted LOW when the device is congured for Full-Duplex operation. The PLED1n output has both pullup and pulldown driver transistors and a weak pullup resistor, so it can drive an LED from either VDD or GND and can also drive a digital input. See Section 2.3.13, "LED Drivers," page 2-28 for more details on how to program the LED output pins to indicate various conditions.
2.6.3 Loopback
2.6.3.1 Internal CRS Loopback TX_EN is internally looped back onto CRS during every transmit packet. This internal CRS loopback is disabled during collision, in Full-Duplex
2-34
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
mode, and in the Link Fail State. In 10 Mbits/s mode, internal CRS loopback is also disabled when jabber is detected. 2.6.3.2 Diagnostic Loopback Setting the loopback bit (LPBK) in the MI serial port Control register selects the diagnostic loopback mode. When diagnostic loopback is enabled, the TXD[3:0] data is looped back onto RXD[3:0], TX_EN is looped back onto CRS, RX_DV operates normally, the TP receive and transmit paths are disabled, the transmit link pulses are halted, and the Half-/Full-Duplex modes do not change.
2.7 10/100 Mbits/s Selection
The device can be forced into either the 10 or 100 Mbits/s mode, or it can use AutoNegotiation to autoselect 10 or 100 Mbits/s operation.
2.7.1 Forcing 10/100 Mbits/s Operation
To independently force each channel into either the 10 Mbits/s or 100 Mbits/s mode clear the ANEG_EN bit in the MI serial port Control register, and set the Speed Select (SPEED) bit in the MI serial port Control register
2.7.2 Autoselecting 10/100 Mbits/s Operation
The device can automatically congure itself for 10 or 100 Mbits/s mode. To do this, it uses the AutoNegotiation algorithm to advertise and detect 10 and 100 Mbits/s capabilities to and from a remote device. Setting the AutoNegotiation Enable (ANEG_EN) bit in the MI serial port Control register enables AutoNegotiation. Appropriately setting the bits in the MI serial port AutoNegotiation Advertisement register selects the advertised speed capability. AutoNegotiation functionality is described in more detail in Section 2.3.10, "Link Integrity and AutoNegotiation".
10/100 Mbits/s Selection
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2-35
2.7.3 10/100 Mbits/s Indication
The channel 10/100 Mbits/s speed can be monitored through the SPD_DET bit in the MI serial port Channel Status Output register. In the MI serial port Conguration register, set the LED function select bits (LED_DEF[1:0]) so that the 10/100 speed condition is indicated at the PLED0n output. Set the PLED_2[1:0]n bits in the same register to 0b11 (normal). When the PLED0n pin is programmed to be a speed detect output, it is asserted LOW when the device is congured for 100 Mbits/s operation. The PLED0n output has both pullup and pulldown driver transistors and a weak pullup resistor, so it can drive an LED from either VDD or GND and can also drive a digital input. See Section 2.3.13, "LED Drivers," page 2-28 for more details on how to program the LED output pins to indicate various conditions.
2.8 Jabber
A jabber condition occurs in 10 Mbits/s mode when the transmit packet exceeds a predetermined length. When jabber is detected, the TP transmit outputs are forced to the idle state, a collision is asserted, and the JAB register bit is set in the MI serial port Status register. Clearing the Jabber Disable (JAB_DIS) bit to 0 in the MI serial port Conguration register disables the jabber function. The jabber function is disabled in the 100 Mbits/s mode.
2.9 Reset
The device is reset when 1. VDD is applied to the device, or 2. the reset bit (RST) is set in the MI serial port Control register, or 3. the RESETn pin is asserted (LOW). When reset occurs because of (1) or (2), an internal power-on reset pulse is generated that resets all internal circuits, forces the MI serial port
2-36
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
bits to their default values, and latches in new values for the MI address. After the power-on reset pulse has nished, the reset bit (RST) in the MI serial port Control register is cleared and the device is ready for normal operation. When reset is initiated because of (3), the same procedure occurs except the device stays in the reset state as long as the RESETn pin is held LOW. The RESETn pin has an internal pullup to VDD. The device is guaranteed to be ready for normal operation 50 ms after the reset sequence is initiated.
2.10 Receive Polarity Correction
In 10 Mbits/s mode, the polarity of the signal on the TP receive input is continuously monitored. A start of idle (SOI) pulse is sent at the end of transmission in order to signal to a receiver that transmission has ended and the idle period has started. The SOI pulse is a positive pulse. When the SOI pulse is detected, it indicates that receive data is no longer valid and causes the device to turn on the receive squelch mechanism. Link pulses are transmitted occasionally during the idle period. When the device is powered up, it is assumed that the polarity is correct and no polarity correction occurs. After that, receive polarity is continuously monitored by checking the polarity of the SOI pulses (they are always expected to be positive pulses). If three consecutive SOI pulses indicate incorrect polarity on the TP receive input, the polarity is internally determined to be incorrect. In this case, the Reverse Polarity Detect bit (RPOL) is set in the MI serial port Status Output register. The device automatically corrects for the reverse polarity condition, provided the autopolarity feature is not disabled. To disable autopolarity, set the Autopolarity Disable bit (APOL_DIS) in the MI serial port Conguration register. No polarity detection or correction is needed in the 100 Mbits/s mode.
Receive Polarity Correction
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2-37
2-38
Functional Description
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 3 Signal Descriptions
This chapter describes the device signals. It contains the following sections: Section 3.1, "Media Interface Signals" Section 3.2, "Controller Interface Signals (MII)" Section 3.3, "Management Interface (MI)/LED Signals" Section 3.4, "LED Signals" Section 3.5, "Miscellaneous Signals" Section 3.6, "Power Supply" Figure 3.1 is a logic diagram for the device.
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3-1
Figure 3.1
Device Logic Diagram
TPI TPI TPO TPO REXT OSCIN CRS TX_CLK TX_EN TX_ER TXD[3:0] RX_CLK RX_EN RXD[3:0] RX_DV RX_ER MDC MDIO MDA4n
Media Interface
Controller Interface (MII)
10/100 Mbit/s Ethernet Physical Layer Device (PHY)
PLED5n PLED4n PLED3n/MDA3n PLED2n/MDA2n PLED1n/MDA1n PLED0n/MDA0n COL RESETn NC SPEED DPLX ANEG
LEDs/ MI Address
Miscellaneous
Management Interface
3.1 Media Interface Signals
REXT
Transmit Current Set
A resistor connected between the REXT pin and GND sets the output current for the TP transmit outputs.
I
TPO+
Twisted-Pair Transmit Output (Positive) The TPO+ pin functions as the positive signal in the twisted-pair output. Twisted-Pair Transmit Output (Negative) The TPO- pin functions as the negative signal in the twisted-pair output.
O
TPO-
O
3-2
Signal Descriptions
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
TPI+
Twisted-Pair Receive Input (Positive) The TPI+ pin functions as the positive signal in the twisted-pair input. Twisted-Pair Receive Input (Negative) The TPI- pin functions as the negative signal in the twisted-pair input.
I
TPI-
I
3.2 Controller Interface Signals (MII)
CRS Carrier Sense Output O The CRS output is asserted HIGH when valid data is detected on the receive TP inputs. CRS is clocked out on the falling edge of RX_CLK. Clock Oscillator Input I There must be either a 25 MHz crystal between this pin and GND or a 25 MHz clock applied to this pin. TX_CLK output is generated from this input. Receive Clock Output O Receive data on RXD, RX_DV, and RX_ER is clocked out to an external controller on the falling edge of RX_CLK. Receive Data Output O RXD[3:0] contain receive nibble data from the TP input, and they are clocked out on the falling edge of RX_CLK. Receive Data Valid Output O RX_DV is asserted HIGH when valid decoded data is present on the RXD outputs. RX_DV is clocked out on the falling edge of RX_CLK. Receive Enable Input I When RX_EN is HIGH, all of the receive outputs (RX_CLK, RXD[3:0], RX_DV, RX_ER, COL) are enabled. When RX_EN is LOW, the outputs are in a high-impedance state. RX_ER Receive Error Output O RX_ER is asserted HIGH when a coding error or other specied errors are detected on the receive twisted-pair inputs. The signal is clocked out on the falling edge of RX_CLK.
OSCIN
RX_CLK
RXD[3:0]
RX_DV
RX_EN
Controller Interface Signals (MII)
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
3-3
TX_CLK
Transmit Clock Output O Transmit data from the controller on TXD, TX_EN, and TX_ER is clocked in on the rising edge of TX_CLK and OSCIN. Transmit Data Input I TXD[3:0] contain input nibble data to be transmitted on the TP outputs, and they are clocked in on the rising edge of TX_CLK and OSCIN when TX_EN is asserted. Transmit Enable Input I TX_EN must be asserted HIGH to indicate that data on TXD and TX_ER is valid. TX_ER is clocked in on the rising edge of TX_CLK and OSCIN. Transmit Error Input I The TXER pin, when asserted, causes a special pattern to be transmitted on the twisted-pair outputs in place of normal data, and it is clocked in on the rising edge of TX_CLK when TX_EN is asserted.
TXD[3:0]
TX_EN
TX_ER
3.3 Management Interface (MI)/LED Signals
MDC MI Clock I The MDC clock shifts serial data for the internal registers into and out of the MDIO pin on its rising edge. Address 4 Input Pullup O.D. I During powerup or reset, this pin is high-impedance and the level on this pin is latched in as the physical device address MDA4 for the MI serial port MDIO MI Data I/O This bidirectional pin contains serial data for the internal registers. The data on this pin is clocked in and out of the device on the rising edge of MDC.
MDA4n
PLED3n/MDA3n Pullup O.D. I/O Programmable LED Output/MI Address Bit The default function of this pin is to be a 100 Mbits/s Link Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user controlled. This pin can drive an LED from VDD.
3-4
Signal Descriptions
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
When programmed as a 100 Mbits/s Link Detect Output (default):
Pin HIGH LOW Function No Link Detect 100 Mbits/s Link Detected
During powerup or reset, this pin is high-impedance and the level on this pin is latched in as the physical device address MDA3n for the MI serial port. PLED2n/MDA2n Pullup O.D. I/O Programmable LED Output/MI Address Bit The default function of this pin is to be an Activity Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user controlled. This pin can drive an LED from VDD. When programmed as an Activity Detect Output (default):
Pin Function
HIGH No Activity LOW Transmit or receive packet occurred (held LOW for 100 ms)
During powerup or reset, this pin is high-impedance and the level on this pin is latched in as the physical device address MDA2n for the MI serial port. PLED1n/MDA1n Pullup O.D. I/O Programmable LED Output/MI Address Bit The default function of this pin is to be a Full Duplex Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user controlled. This pin can drive an LED from both VDD and GND. When programmed as Full Duplex Detect Output (default):
Pin HIGH LOW Function Half-Duplex Full-Duplex
Management Interface (MI)/LED Signals
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
3-5
During powerup or reset, this pin is high-impedance and the level on this pin is latched in as the physical address device address MDA1n for the MI serial port. PLED0n/MDA0n Pullup O.D. I/O Programmable LED Output/MI Address Bit The default function of this pin is to be a 10 Mbits/s Link Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user controlled. This pin can drive an LED from both VDD and GND. When programmed as 10 Mbits/s Link Detect Output (default):
Pin HIGH LOW Function No Detect 10 Mbits/s Link Detected
During powerup or reset, this pin is high-impedance and the value on this pin is latched in as the address MDA0n for the MI serial port.
3.4 LED Signals
PLED5n Receive LED Output Pullup O.D. O The function of this pin is to be a Receive Activity Detect output. This pin can also drive an LED from VDD. HIGH = No Receive Activity LOW = Receive packet occurred: hold LOW for 100 ms PLED4n Transmit LED Output Pullup O.D. O The function of this pin is to be a Transmit Activity Detect output. This pin can also drive an LED from VDD. HIGH = No Transmit Activity LOW = Transmit packet occurred: hold LOW for 100 ms
3-6
Signal Descriptions
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
3.5 Miscellaneous Signals
ANEG AutoNegotiation Input This pin control AutoNegotiation operation.
Pin HIGH Meaning AutoNegotiation is on. AutoNegotiation Enable is controlled from the ANEG_EN bit, 10/100 Mbits/s operation is controlled from the SPEED bit, and Half/Full Duplex operation is controlled from the DPLX bit. AutoNegotiation is off. 10/100 Mbits/s operation is controlled from the SPEED pin and Half/Full Duplex operation is controlled from the DPLX pin.
I
LOW
COL
Collision Output O COL is asserted HIGH when a collision between transmit and receive data is detected. Full/Half Duplex Select Input When the ANEG pin is LOW, the DPLX pin selects Half/Full Duplex operation.
Pin HIGH LOW Meaning Full Duplex operation Half Duplex operation
DPLX
I
When the ANEG pin is HIGH, the DPLX pin is ignored and the Half/Full Duplex operation is controlled from the Duplex Mode Select bit (DPLX) in the MI serial port Control register or the AutoNegotiation outcome. NC No Connect These pins are reserved for future use and should be left oating for proper operation. Hardware Reset Input
Pin HIGH LOW Meaning Normal Device in reset state. Reset is nished 100 ms after RESETn goes HIGH.
RESETn
Pullup I
Miscellaneous Signals
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
3-7
SPEED
Speed Select Input When the ANEG pin is LOW, the SPEED pin selects 10/100 Mbits/s operation.
Pin HIGH LOW Meaning 100 Mbits/s operation 10 Mbits/s operation
I
When the ANEG pin is HIGH, this pin is ignored and the speed is determined from the Speed Select bit (SPEED) in the MI serial port Control register or the AutoNegotiation outcome.
3.6 Power Supply
GND VDD Ground I The ground pins must be connected to ground (0 Volts). Positive Supply The VDD pins must be connected to 3.3 I 5% Volts.
3-8
Signal Descriptions
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 4 Registers
This chapter contains a description of the registers accessed over the management interface (MI) serial interface. It contains the following sections: Section 4.1, "Bit Types" Section 4.2, "MI Serial Port Register Summary" Section 4.3, "Registers" For further information about the operation of the MI serial interface, see Chapter 5, "Management Interface."
4.1
Bit Types
Because the serial port is bidirectional (capable of both read and write operations), there are many types of bits. The following bit type denitions are summarized in Table 4.1: Write bits (W) are inputs during a write cycle and are high impedance during a read cycle Read bits (R) are outputs during a read cycle and high impedance during a write cycle Read/Write bits (R/W) are actually write bits that can be read out during a read cycle R/WSC bits are R/W bits that are self-clearing after a set period of time or after a specic event has completed R/LL bits are read bits that latch themselves when they go LOW, and they stay LOW until read. After they are read, they are reset HIGH. R/LH bits are the same as R/LL bits, except that they latch HIGH.
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4-1
R/LT are read bits that latch themselves whenever they make a transition or change value, and they stay latched until they are read. After R/LT bits are read, they are updated to their current value. Table 4.1 MI Register Bit Type Denition
Denition Symbol W R R/W R/WSC R/LL Name Write Read Read/Write Read/Write, Self-Clearing Read/Latching LOW Read/Latching HIGH Read/Latching on transition Write Cycle Input No operation, Hi-Z Input Input No operation, Hi-Z Read Cycle No operation, Hi-Z Output Output Output (clears itself after the operation completes) Output When the bit goes LOW, it is latched. When the bit is read, it is updated. Output When the bit goes HIGH, it is latched. When the bit Is read, it is updated. Output When the bit transitions, the bit is latched. When the bit is read, the bit is updated.
R/LH
No operation, Hi-Z
R/LT
No operation, Hi-Z
4-2
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4.2
MI Serial Port Register Summary
The following tables summarize the device registers accessible through the MI serial port.
Control Register (Register 0)
15 RST 7 COLTST 14 LPBK 6 Reserved 13 SPEED 12 ANEG_EN 11 PDN 10 MII_DIS 9 ANEG_RST 8 DPLX 0
Status Register (Register 1)
15 CAP_T4 7 Reserved 14 CAP_TXF 6 CAP_SUPR 13 CAP_TXH 5 ANEG_ACK 12 CAP_TF 4 REM_FLT 11 CAP_TH 3 CAP_ANEG 2 LINK 10 Reserved 1 JAB 0 EXREG 8
PHY ID #1 Register (Register 2) -
15 OUI3 7 OUI11 14 OUI4 6 OUI12 13 OUI5 5 OUI13 12 OUI6 4 OUI14 11 OUI7 3 OUI15 10 OUI8 2 OUI16 9 OUI9 1 OUI17 8 OUI10 0 OUI18
PHY ID #2 Register (Register 3)
15 OUI19 7 PART3 14 OUI20 6 PART2 13 OUI21 5 PART1 12 OUI22 4 PART0 11 OUI23 3 REV3 10 OUI24 2 REV2 9 PART5 1 REV1 8 PART4 0 REV0
MI Serial Port Register Summary
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-3
AutoNegotiation Advertisement Register (Register 4)
15 NP 7 TX_HDX 14 ACK 6 10_FDX 13 RF 5 10_HDX 4 Reserved 12 Reserved 10 9 T4 1 8 TX_FDX 0 CSMA
AutoNegotiation Remote End Capability Register (Register 5)
15 NP 7 TX_HDX 14 ACK 6 10_FDX 13 RF 5 10_HDX 4 Reserved 12 Reserved 10 9 T4 1 8 TX_FDX 0 CSMA
Conguration Register (Register 17)
15 PLED3_1 7 LED_DEF1 LED_DEF0 APOL_DIS 14 PLED3_0 13 PLED2_1 12 PLED2_0 4 JAB_DIS 11 PLED1_1 3 MREG 10 PLED1_0 2 9 PLED0_1 1 Reserved 8 PLED0_0 0
Status Output Register (Register 18)
15 Reserved 7 Reserved 5 4 SPD_DET 3 DPLX_DET 2 Reserved 0 8
4-4
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4.3
Registers
This section contains a description of each of the bits in each register.
4.3.1
Control Register (Register 0)
The default value for this register is 0x3400.
15 RST 7 COLTST
14 LPBK 6
13 SPEED
12 ANEG_EN
11 PDN
10 MII_DIS
9 ANEG_RST
8 DPLX 0
Reserved
RST
Reset
Bit 1 0 Meaning
R/WSC 15
Reset. The bit is bit self-clearing in less than or equal to 200 s after reset nishes. Normal (Default)
LPBK
Loopback Enable
Bit 1 0 Meaning Loopback mode enabled Normal (Default)
R/W 14
SPEED
Speed Select
Bit1 1 0 Meaning 100 Mbit/s (100BASE-TX) (default) 10 Mbit/s (10BASE-T)
R/W 13
1. The SPEED bit is effective only when AutoNegotiation is off
ANEG_EN
AutoNegotiation Enable
Bit 1 0 Meaning 1 = AutoNegotiation enabled (default) 0 = Disabled
R/W 12
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-5
PDN
Power Down Enable
Bit 1 0 Meaning Power down Normal (default)
R/W 11
MII_DIS
MII Interface Disable
Bit1 0 1 Meaning MII interface disable Normal (default)
R/W 10
1. If MDA[4:0]n is not read as 0b11111, the MII_DIS default value is changed to 0.
ANEG_RST
AutoNegotiation Reset
Bit 1 0 Meaning
R/WSC 9
Restart AutoNegotiation process. The bit is self-clearing after reset is nished Normal (default)
DPLX
Duplex Mode Select
Bit1 1 0 Meaning Full-duplex (default) Half-duplex
R/W 8
1. This bit is effective only when AutoNegotiation is off
COLTST
Collision Test Enable
Bit 1 0 Meaning Collision test enabled Normal (default)
R/W 7
R
Reserved R [6:0] These bits are reserved and must remain at the default value of 0x00 for proper device operation.
4-6
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4.3.2
Status Register (Register 1)
The default value of this register is 0x7809.
15 CAP_T4 7 Reserved
14 CAP_TXF 6 CAP_SUPR
13 CAP_TXH 5 ANEG_ACK
12 CAP_TF 4 REM_FLT
11 CAP_TH 3 CAP_ANEG
10 Reserved 2 LINK 1 JAB
8
0 EXREG
CAP_T4
100BASE-T4 Capable
Bit 1 0 Meaning Capable of 100BASE-T4 operation Not capable of 100BASE-T4 Operation (default)
R 15
CAP_TXF
100BASE-TX Full Duplex Capable
Bit 1 0 Meaning Capable of 100BASE-TX Full-Duplex (default) Not capable of 100BASE-TX Full-Duplex
R 14
CAP_TXH
100BASE-TX Half Duplex Capable
Bit 1 0 Meaning Capable of 100BASE-TX Half-Duplex (default) Not capable of 100BASE-TX Half-Duplex
R 13
CAP_TF
10BASE-T Full Duplex Capable
Bit 1 0 Meaning Capable of 10BASE-T Full-Duplex (default) Not capable of 10BASE-T Full-Duplex
R 12
CAP_TH
10BASE-T Half Duplex Capable
Bit 1 0 Meaning Capable of 10BASE-T Half Duplex (default) Not capable of 10BASE-T Half Duplex
R 11
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-7
R
Reserved R [10:7] These bits are reserved and must remain at the default value of 0x0 for proper device operation MI Preamble Suppression Capable
Bit 1 0 Meaning Capable of accepting MI frames with preamble suppression Not capable of accepting MI frames with preamble suppression (default)
CAP_SUPR
R6
ANEG_ACK
AutoNegotiation Acknowledgment
Bit 1 0 Meaning AutoNegotiation acknowledgment process complete AutoNegotiation not complete (default)
R5
REM_FLT
Remote Fault Detect
Bit 1 Meaning
R/LH 4
Remote fault detect. The REM_FLT bit is set when Remote Fault (RF) bit is set in the AutoNegotiation Remote End Capability register. No remote fault (default)
0
CAP_ANEG
AutoNegotiation Capable
Bit 1 0 Meaning Capable of AutoNegotiation (default) Not capable of AutoNegotiation
R3
LINK
Link Status
Bit 1 0 Meaning Link detected. Link not detected (default)
R/LL 2
4-8
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
JAB
Jabber Detect
Bit 1 0 Meaning Jabber detected Normal (default)
R/LH 1
EXREG
Extended Register Capable
Bit 1 0 Meaning Extended registers exist (default) Extended registers do not exist
R0
4.3.3
15 OUI3 7 OUI11
PHY ID 1 Register (Register 2)
14 OUI4 6 OUI12 13 OUI5 5 OUI13 12 OUI6 4 OUI14 11 OUI7 3 OUI15 10 OUI8 2 OUI16 9 OUI9 1 OUI17 8 OUI10 0 OUI18
OUI[3:18]
Company ID, Bits 3-18 R [15:0] OUI[3:18] in this register and OUI[19:24] of the PHY ID 2 register make up the LSI OUI, whose default value is 0x00.A07D. The table below shows the default bit positions for the entire OUI eld:
Bit OIU24 OIU23 OIU22 OIU21 OIU20 OIU19 OIU18 OIU17 OIU16 OIU15 OIU14 OIU13 OIU12 OIU11 OIU10 OIU9 Default Value 0 1 1 1 1 1 0 1 1 0 1 0 0 0 0 0 Hex Value 0x7
0xD
0xA
0x0
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-9
Bit OIU8 OIU7 OIU6 OIU5 OIU4 OUI3
Default Value 0 0 0 0 0 0
Hex Value 0x0
0x0
4.3.4
15 OUI19 7 PART3
PHY ID 2 Register (Register 3)
14 OUI20 6 PART2 13 OUI21 5 PART1 12 OUI22 4 PART0 11 OUI23 3 REV3 10 OUI24 2 REV2 9 PART5 1 REV1 8 PART4 0 REV0
OUI[19:24]
Company ID, Bits 19-24 R [15:10] OUI[19:24] in this register and OUI[3:18] of the PHY ID 1 register make up the LSI OUI, whose default value is 0x00.A07D. See the table in the PHY ID 1 description for a description of the entire OUI eld. Manufacturer's Part Number R [9:4] The default value for this eld is 0x04. The table below shows the default bit positions for the PART[5:0] eld:
Bit PART[5] PART[4] PART[3] PART[2] PART[1] PART[0] Default Value 0 0 0 1 0 0 0x4 Hex Value 0x0
PART[5:0]
REV[3:0]
Manufacturer's Revision Number The default value for this eld is 0x0.
R [3:0]
4-10
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4.3.5
AutoNegotiation Advertisement Register (Register 4)
The default value for this register is 0x01E1.
15 NP 7 TX_HDX
14 ACK 6 10_FDX
13 RF 5 10_HDX
12 Reserved 4 Reserved
10
9 T4 1
8 TX_FDX 0 CSMA
NP
Next Page Enable
Bit 1 0 Meaning Next page No next page (default)
R 15
ACK
Acknowledge
Bit 1 0 Meaning AutoNegotiation word recognized Not recognized (default)
R 14
RF
Remote Fault
Bit 1 0 Meaning AutoNegotiation remote fault detect No remote fault detect (default)
R/W 13
R
Reserved R/W[12:10] These bits are reserved and must remain at the default value of 0b00 for proper device operation 100BASE-T4 Capable
Bit 1 0 Meaning Capable of 100BASE-T4 operation Not capable (default)
T4
R/W 9
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-11
TX_FDX
100BASE-TX Full Duplex Capable
Bit 1 0 Meaning
R/W 8
Capable of 100BASE-TX Full Duplex operation (default) Not capable
TX_HDX
100BASE-TX Half Duplex Capable
Bit 1 0 Meaning
R/W 7
Capable of 100BASE-TX Half Duplex operation (default) Not capable
10_FDX
10BASE-TX Full Duplex Capable
Bit 1 0 Meaning
R/W 6
Capable of 10BASE-T Full-Duplex operation (default) Not capable
10_HDX
10BASE-TX Half Duplex Capable
Bit 1 0 Meaning
R/W 5
Capable of 10BASE-T Half-Duplex operation (default) Not capable
R
Reserved R/W [4:1] These bits are reserved and must remain at the default value of 0x0 for proper device operation CSMA 802.3 Capable
Bit 1 0 Meaning Capable of 802.3 CSMA1 operation (default) Not capable
CSMA
R/W 0
1. Carrier-Sense, Multiple-Access
4-12
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4.3.6
AutoNegotiation Remote End Capability Register (Register 5)
The default value for this register is 0x0000.
15 NP 7 TX_HDX
14 ACK 6 10_FDX
13 RF 5 10_HDX
12 Reserved 4 Reserved
10
9 T4 1
8 TX_FDX 0 CSMA
NP
Next Page Enable
Bit 1 0 Meaning Next Page exists No Next Page (default)
R 15
5
ACK
Acknowledge
Bit 1 0 Meaning Received AutoNegotiation Word recognized Not Recognized (default)
R 14
RF
Remote Fault
Bit 1 0 Meaning AutoNegotiation Remote Fault detect No Remote Fault (default)
R 13
R
Reserved
R [12:10]
These bits are reserved and must remain at the default value of 0b00 for proper device operation T4 100BASE-T4 Capable
Bit 1 0 Meaning Capable of 100BASE-T4 operation Not capable (default)
R9
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-13
TX_FDX
100BASE-TX Full Duplex Capable
Bit 1 0 Meaning Capable of 100BASE-TX Full Duplex operation Not capable (default)
R8
TX_HDX
100BASE-TX Half Duplex Capable
Bit 1 0 Meaning Capable of 100BASE-TX Half Duplex operation Not capable (default)
R7
10_FDX
10BASE-TX Full Duplex Capable
Bit 1 0 Meaning Capable of 10BASE-T Full Duplex operation Not capable (default)
R6
10_HDX
10BASE-TX Half Duplex Capable
Bit 1 0 Meaning Capable of 10BASE-T Half Duplex operation Not capable (default)
R5
R
Reserved R [4:1] These bits are reserved and must remain at the default value of 0x0 for proper device operation CSMA 802.3 Capable
Bit 1 0 Meaning Capable of 802.3 CSMA1 Operation Not capable (default)
CSMA
R0
1. Carrier-Sense, Multiple-Access
4-14
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4.3.7
Conguration Register (Register 17)
The default value for this register is 0xFF00.
15 PLED3_1n 7 LED_DEF1
14 PLED3_0n
13 PLED2_1n
12 PLED2_0n 4
11 PLED1_1n 3 MREG
10 PLED1_0n 2
9 PLED0_1n 1 Reserved
8 PLED0_0n 0
LED_DEF0
APOL_DIS
JAB_DIS
PLED3_[1:0]n Programmable LED 3 Output Select
PLED3_1n PLED3_0n Meaning 1 1
R/W [15:14]
Normal: PLED3n pin state is determined from the LED_DEF[1:0] bits (default is LINK100). 0b11 is the default for these bits LED tied to PLED3n blinks (toggles 100 ms LOW, then 100 ms HIGH) LED tied to PLED3n ON steady (PLED3n output LOW) LED tied to PLED3n OFF steady (PLED3n output HIGH)
1 0 0
0 1 0
PLED2_[1:0]n Programmable LED 2 Output Select
PLED2_1n PLED2_0n Meaning 1 1
R/W [13:12]
Normal: PLED2n pin state is determined from the LED_DEF[1:0] bits (default is Activity). 0b11 is the default for these bits LED tied to PLED2n blinks (toggles 100 ms LOW, then 100 ms HIGH) LED tied to PLED2n ON steady (PLED2n output LOW) LED tied to PLED2n OFF steady (PLED2n output HIGH)
1 0 0
0 1 0
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-15
PLED1_[1:0]n Programmable LED 1 Output Select
PLED1_1n PLED1_0n Meaning 1 1
R/W [11:10]
Normal: PLED1n pin state is determined from the LED_DEF[1:0] bits (default is Full-Duplex). 0b11 is the default for these bits LED tied to PLED1n blinks (toggles 100 ms LOW, then 100 ms HIGH) LED tied to PLED1n ON steady (PLED1n output LOW) LED tied to PLED1n OFF steady (PLED1n output HIGH)
1 0 0
0 1 0
PLED0_[1:0]n Programmable LED 0 Output Select
PLED3_1n PLED3_0n Meaning 1 1
R/W [9:8]
Normal: PLED0n pin state is determined from the LED_DEF[1:0] bits (default is Link 10). 0b11 is the default for these bits LED tied to PLED0n blinks (toggles 100 ms LOW, then 100 ms HIGH) LED tied to PLED0n ON steady (PLED0n output LOW) LED tied to PLED0n OFF steady (PLED0n output HIGH)
1 0 0
0 1 0
LED_DEF_[1:0] LED Normal Function Select R/W [7:6] See Table 2.7 on page 2-29 for these bit denitions. APOL_DIS Autopolarity Disable
Bit 1 0 Meaning Autopolarity correction disabled Normal (default)
R5
4-16
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
JAB_DIS
Jabber Disable
Bit 1 0 Meaning Jabber disabled Jabber enabled (default)
R4
MREG
Multiple Register Access Enable
Bit 1 0 Meaning Multiple register access enabled No multiple register access (default)
R3
R
Reserved R [2:0] These bits are reserved and must remain at the default value of 0x0 for proper device operation.
4.3.8
Channel Status Output 0 Register (Register 18)
The default value for this register is 0x0000.
15 Reserved 7 SPD_DET 6 DPLX_DET 5 Reserved
8
0
SPD_DET
100/10 Mbits/s Speed Detect
Bit 1 0 Meaning Device is in 100 Mbits/s mode (100BASE-TX) Device is in 10 Mbits/s mode (10 BASE-T)
R7
DPLX_DET
Duplex Detect
Bit 1 0 Meaning Device is operating in Full-Duplex Device is operating in Half-Duplex
R6
R
Reserved R [5:0] These bits are reserved and must remain at the default value of 0x0 for proper device operation.
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
4-17
4-18
Registers
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 5 Management Interface
This chapter describes the Management Interface, over which the internal device registers are accessed. It contains the following sections: Section 5.1, "Signal Description" Section 5.2, "General Operation" Section 5.3, "Frame Structure" Section 5.4, "Register Structure" The Management Interface, referred to as the MI serial port, is a 7-pin bidirectional link through which the internal device registers are accessed. The internal register bits control the conguration and capabilities of the device, and reect device status. The MI serial port provides access to eight internal registers and meets all IEEE 802.3 specications for the Management Interface.
5.1 Signal Description
The MI serial port has six pins: MDC - serial shift clock input pin MDIO - bidirectional data pin MDA[3:0]n - physical address pins The MDA[3:0]n pins congure the device for a particular address, from 0b0000 to 0b1111, such that 16 devices can exist in the same address domain and each can be addressed separately over the MI serial port. When an MI read or write cycle occurs, the device compares the internally inverted and latched state of the MDA[4:0]n pins to the
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
5-1
PHYAD[4:0] address bits of the MI frame. If the states compare, the device knows it is being addressed. The MDA[3:0]n inputs share the same pins as the PLED[3:0]n LED outputs, respectively. At powerup or reset, the LED output drivers are 3-stated for an interval called the power-on reset time. During the power-on reset time, the level of these pins is latched into the device, inverted, and used as the MI serial port physical device address.
5.2 General Operation
The MI serial port is idle when at least 32 continuous 1s are detected on the bidirectional MDIO data pin and remains idle as long as continuous 1s are detected. During idle, the MDIO output driver is in the highimpedance state. When the MI serial port is in the idle state, a 0b01 pattern on the MDIO pin initiates a serial shift cycle. Control and address bits are clocked into MDIO on the next 14 rising edges of MDC (the MDIO output driver is still in a high-impedance state). If multiple register access is not enabled, data is either shifted in or out on MDIO on the next 16 rising edges of MDC, depending on whether a write or read cycle was selected with the READ and WRITE operation bits. After the 32 MDC cycles have been completed one complete register has been read or written the serial shift process is halted data is latched into the device the MDIO output driver goes into a high-impedance state. Another serial shift cycle cannot be initiated until the idle condition is detected again (at least 32 continuous 1s). Figure 5.1 shows a timing diagram for a MI serial port cycle.
5-2
Management Interface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 5.1
MI Serial Port Frame Timing Diagram
WRITE Cycle
MDC
Rev. B
MDIO
General Operation
OP PHYAD REGAD TA DATA WRITE Bits PHY clocks in data on rising edges of MDC with ts = 10 ns minimum and th = 10 ns minimum OP PHYAD REGAD TA DATA READ Bits PHY clocks out data on rising edges of MDC with td = 20 ns maximum
ST
READ Cycle
MDC
MDIO
ST
WRITE Bits PHY clocks in data on rising edges of MDC with ts = 10 ns minimum, and th = 10 ns minimum
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Note: ST = start bits, OP = operation bits (read or write), PHAD = PHY address, REGAD = register address, TA = turnaround bits For more detailed information on the timing related to ts, th, and td, please see Chapter 6, "Specications."
5-3
5.3 Frame Structure
The structure of the serial port frame is shown in Figure 5.2 and a timing diagram is shown in Figure 5.1. Each serial port access cycle consists of 32 bits (or 144 bits if multiple register access is enabled and REGAD[4:0] = 0b11111), exclusive of idle. The rst 16 bits of the serial port cycle are always write bits and are used for control and addressing. The last 16 bits are data that is written to or read from a data register. The rst two bits in Figure 5.2 and Figure 5.1 are start bits (ST[1:0]) and must be written as a 0b01 for the serial port cycle to continue. The next two bits are the READ and WRITE bits, which determine whether the registers are being read or written. The next ve bits are the PHY device address bits (PHYAD[4:0]), and they must match the inverted values latched from the MDA[4:0]n pins during the power on reset time for access to continue. The next ve bits are register address select (REGAD[4:0]) bits, which select one of the eight registers for access. The next two bits are turnaround (TA) bits, which are not actual register bits but provide the device extra time to switch the MDIO pin function from a write pin to a read pin, if necessary. The nal 16 bits of the MI serial port cycle are written to or read from the specic data register that the register address bits (REGAD[4:0]) designate. Figure 5.2 shows the MI frame structure.
Figure 5.2
IDLE
MI Serial Frame Structure
READ WRITE PHYAD[4:0] REGAD[4:0] TA[1:0] D[15:0]
ST[1:0]
IDLE
Idle Pattern W These bits are an idle pattern. The device does not initiate an MI cycle until it detects an idle pattern of at least 32 consecutive 1s. Start Bits W When ST[1:0] = 01, a MI serial port access cycle starts. Read Select When the READ bit is 1, it designates a read cycle. W
ST[1:0] READ
5-4
Management Interface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
WRITE PHYAD[4:0]
Write Select W When the WRITE bit is 1, it designates a write cycle. Physical Device Address W When the PHYAD[4:0] bits match the inverted latched value of the MDA[4:0]n pins, the device's MI serial port is selected for operation. Register Address W The REGAD[4:0] bits determine the specic register to access. Turnaround Time R/W These bits provide some turnaround time for MDIO to allow it to switch to a write input or read output, as needed. When READ = 1, TA[1:0] = Z0; when WRITE = 1, TA[1:0] = 0b10. Data R or W These 16 bits contain data to or from one of the registers selected with the register address bits REGAD[4:0].
REGAD[4:0]
TA[1:0]
D[15:0]
5.4 Register Structure
The device has eight 16-bit registers. A map of the registers is shown in Section 4.2, "MI Serial Port Register Summary". See Chapter 4, Registers for a complete description of each register. The eight registers consist of six registers that are dened by IEEE 802.3 specications (registers 0 to 5) and two registers that are unique to the device (registers 17 and 18). Table 5.1 gives a summary of the functions of each register
Register Structure
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
5-5
.
Table 5.1
Register 0 1 2 3 4 5
MI Serial Port Register Summary
Name Control Register Status Register PHY ID 1 PHY ID 2 AutoNegotiation Advertisement AutoNegotiation Remote End Capability Conguration Channel Status Output 0 Contains bits that control the operation of the AutoNegotiation algorithm Contains bits that reect the AutoNegotiation capabilities of the link partner's PHY Stores various conguration bits Contains status Description Stores various conguration bits Contains device capability and status output bits Contain an identication code unique to the device
17 18
5-6
Management Interface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 6 Specications
This chapter contains the complete electrical, timing, and mechanical specications for the device. It contains the following sections: Section 6.1, "Absolute Maximum Ratings" Section 6.2, "Electrical Characteristics" Section 6.3, "AC Electrical Characteristics" Section 6.4, "Pinouts and Package Drawings" Section 6.5, "Mechanical Drawing"
6.1 Absolute Maximum Ratings
Table 6.1 shows the device absolute maximum ratings. These are limits which, if exceeded, could cause permanent damage to the device or affect device reliability. All voltages are specied with respect to GND unless otherwise specied. Table 6.1
Parameter VDD Supply Voltage All Inputs and Outputs Package Power Dissipation Storage Temperature Temperature Under Bias Commercial Temperature Industrial Temperature Lead Temperature (soldering, 10 sec) Body Temperature (soldering, 30 sec)
Absolute Maximum Ratings
Range 0.3V to +4.0V 0.3V to 5.5V 2.0 @ 70C 65 to +150 10 to +80 -10 to +80 -40 to +85 260 220 Units V V W C C C C C C
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-1
6.2 Electrical Characteristics
Table 6.2 lists the device DC electrical characteristics. Unless otherwise noted, all test conditions are as follows: TA = 0 to + 70 C (commercial), -40 to + 85 C (industrial) VDD = 3.3 V 5% Clock = 25 MHz + 0.01% REXT = 10 K + 1%, no load Table 6.2 DC Characteristics
Limit Sym VIL Parameter Input Low Voltage Min Typ Max 0.8 VDD 1.5 VIH Input High Voltage VDD 2 200 5.5 1.0 Unit Volt Volt Volt Volt mV Volt 1 4 12 25 120 150 IIH Input High Current 1 150 VOL Output Low Voltage 0.4 1 A A A A A A Volt Volt Conditions All except OSCIN, MDA[3:0]n MDA[3:0]n OSCIN All except OSCIN, MDA[3:0]n MDA[3:0]n OSCIN VIN=GND. All except OSCIN, MDA[3:0]n, RESETn VIN = GND. MDA[3:0]n VIN = GND. VIN = GND. RESETn OSCIN
2.3 IIL Input Low Current
VIN = VDD. All except OSCIN VIN = VDD. OSCIN IOL = 4 mA. All except PLED[5:0]n IOL = 10 mA. PLED[5:0]n
6-2
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 6.2
DC Characteristics (Cont.)
Limit
Sym VOH
Parameter Output High Voltage
Min VDD 2.4 VDD 1.0 1.0
Typ
Max
Unit Volt Volt Volt
Conditions IOH = 4 mA. All Except PLED[5:0]n IOH = 4 A. PLED[5:2]n IOH = 10mA. PLED[1:0]n
CIN IDD
Input Capacitance VDD Supply Current GND Supply Current
5 120 140
pF mA mA mA mA A Transmitting, 100 Mbits/s Transmitting, 10 Mbits/s Transmitting, 100 Mbits/s1, Note 1 Transmitting, 10 Mbits/s1 Powerdown, either IDD or IGND
IGND
190 220
IPDN
Powerdown Supply Current
200
1. IGND includes current owing into GND from the external resistors and transformer on TPO as shown in Figure A.1
6.2.1 Twisted-Pair DC Characteristics
Unless otherwise noted, all test conditions for TP transmit and receive operations are as follows: TA = 0 to + 70 C (commercial), -40 to + 85 C (industrial) VDD = 3.3 V 5% Clock = 25 MHz .01% REXT = 10 K %, no load TPO+/- loading is as shown in Figure A.1 or equivalent 62.5/10 MHz Square Wave on TP+/- inputs in 100/10 Mbits/s modes Table 6.3 shows the twisted-pair characteristics for transmit operation.
Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-3
Table 6.3
Twisted Pair Characteristics (Transmit)
Limit
Sym TOV
Parameter TP Differential Output Voltage
Min
Typ
Max
Unit V pk V pk %
Conditions 100 Mbits/s, UTP mode, 100 ohm load 10 Mbits/s, UTP mode, 100 ohm load 100 Mbits/s, ratio of positive and negative amplitude peaks on TPO 100 Mbits/s 100 Mbits/s, difference between rise and fall times on TPO 100 Mbits/s, output data = 0b 0101... NRZ pattern unscrambled, measure at 50% points 100 Mbits/s, output data = scrambled /H/ 100 Mbits/s 10 Mbits/s 10 Mbits/s 10 Mbits/s, NLP and FLP
0.950 1.000 1.050 2.2 2.5 2.8 102
TOVS
TP Differential Output Voltage Symmetry TP Differential Output Rise And Fall Time TP Differential Output Rise And Fall Time Symmetry TP Differential Output Duty Cycle Distortion
98
TORF TORFS
3.0
5.0 0.5
ns ns
TODC
0.25
ns
TOJ TOO TOVT TSOI TLPT
TP Differential Output Jitter TP Differential Output Overshoot TP Differential Output Voltage Template TP Differential Output SOI Voltage Template TP Differential Output Link Pulse Voltage Template TP Differential Output Idle Voltage TP Output Current 38 88 40 100
1.4 5.0 See Figure 2.4 See Figure 2.6 See Figure 2.7
ns %
TOIV
50
mV
10 Mbits/s. measured on secondary side of transformer in Figure A.1. 100 Mbits/s
TOIA TOIR
42 112 1.2
mA pk
mA pk 10 Mbits/s VDD = 3.3 V, adjustable with REXT, relative to TOIA with REXT = 10 K Ohm pF
TP Output Current Adjustment Range TP Output Resistance TP Output Capacitance
0.80
TOR TOC
10 K 15
6-4
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 6.4 shows the twisted-pair characteristics for receive operation. Table 6.4 Twisted Pair Characteristics (Receive)
Limit Sym RST RUT ROCV RCMR RDR RIR RIC Parameter TP Input Squelch Threshold TP Input Unsquelch Threshold TP Input Open Circuit Voltage TP Input CommonMode Voltage Range TP Input Differential Voltage Range TP Input Resistance TP Input Capacitance 5K 10 Min 166 310 100 186 VDD ROCV 2.4 0.2 0.25 VDD Volt Ohm pF Typ Max 500 540 300 324 Unit Conditions
mV pk 100 Mbits/s, RLVL = 0 mV pk 10 Mbits/s, RLVL = 0 mV pk 100 Mbits/s, RLVL = 0 mV pk 10 Mbits/s, RLVL = 0 Volt Voltage on either TPI+ or TPI with respect to GND. Voltage on TPI with respect to GND.
Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-5
6.3 AC Electrical Characteristics
Unless otherwise noted, all test conditions are as shown in Table 6.5. Table 6.5 Test Conditions
Parameter TA TA VDD REXT tr, tf Value 0 to +70 C -40 to +85 C 3.3V 5%
Test Condition Temperature (commercial) Temperature (industrial) Voltage Clock Frequency External Resistor Input Conditions (all inputs) Output Loading TPO Open-drain outputs All other digital outputs Measurement Points TPO ,TPI All other inputs and outputs
25 MHz 0.01% 10K 1%, no load 10 ns, 20-80% points
Same as Figure A.1 or equivalent
10 pF 1K pullup, 50 pF 25 pF
0.0 V during data, 0.3 V at start/end of packet 1.4 V
6-6
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6.3.1 25 MHz Input/Output Clock Timing Characteristics
Table 6.6 shows the 25 MHz input/Output Clock timing parameters. See Figure 6.1 for the timing diagram. Table 6.6 25 MHz Input/Output Clock
Limit Sym t1 t2 t3 t4 Parameter OSCIN Period OSCIN High Time OSCIN Low Time OSCIN to TX_CLK Delay Min 39.996 16 16 10 20 Typ 40 Max 40.004 Unit ns ns ns ns ns Conditions Clock applied to OSCIN Clock applied to OSCIN Clock applied to OSCIN 100 Mbits/s 10 Mbits/s
Figure 6.1
25 MHz Output Timing
t1 t2 t3
OSCIN t4 TX_CLK (100 Mbits/s) t4 TX_CLK (10 Mbits/s) t4
6.3.2 Transmit Timing Characteristics
Table 6.7 shows the Transmit AC timing parameters. See Figure 6.2 and Figure 6.3 for the 100 Mbits/s and 10 Mbits/s transmit timing diagrams.
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-7
Table 6.7
Transmit Timing
Limit
Sym t11
Parameter TX_CLK Period
Min 39.996
Typ 40
Max 40.004
Unit ns ns ns ns ns ns ns ns ns
Conditions 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s Note1
399.96 400 400.04 t12 TX_CLK Low Time 16 160 t13 TX_CLK High Time 16 160 t14 t15 t16 t17 TX_CLK Rise/Fall Time TX_EN Setup Time TX_EN Hold Time CRS During Transmit Assert Time 15 0 40 400 t18 CRS During Transmit Time TXD Setup Time TXD Hold Time TX_ER Setup Time TX_ER Hold Time Transmit Propagation Delay Deassert 160 900 15 0 15 0 60 140 600 t24 Transmit Output Jitter 0.7 5.5 t25 t26 t27 t28 Transmit SOI Pulse Width To 0.3 V Transmit SOI Pulse Width to 40 mV PLEDn Delay Time PLEDn Pulse Width 80 250 4500 25 105 20 200 20 200 24 240 24 240 10
ns ns ns ns ns ns ns ns ns ns ns pk-pk ns pk-pk ns ns ms ms
100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s Note 1
t19 t20 t21 t22 t23
Note 1
100 Mbits/s, MII 10 Mbits/s 100 Mbits/s 10 Mbits/s 10 Mbits/s 10 Mbits/s PLEDn programmed for activity PLEDn programmed for activity
1. Setup time measured with 5 pF loading on TXC. Additional leading will create delay on TXC rise time which will require increased setup times.
6-8
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 6.2
MI 100 Mbits/s
Transmit Timing (100 Mbits/s)
t11
TX_CLK t15 TX_EN t17 CRS t19 TXD[3:0] N0 N1 t21 TX_ER t23 TPO FXO IDLE t27 t28 PLEDn IDLE /J/K/ t24 DATA /T/R/ IDLE N2 t20 N3 t22 t18 t16 t12 t13 t14 t14
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-9
Figure 6.3
MI 10 Mbits/s
Transmit Timing (10 Mbits/s)
t11
TX_CLK t15 TX_EN t17 CRS t19 TXD[3:0] N0 N1 t23 TP0 t27 PLEDn
PREAMBLE
t16
t12
t13 t14
t14
t18
t20 N2 N3 t24
PREAMBLE
t25 DATA DATA SOI
t26
t28
6-10
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6.3.3 Receive Timing Characteristics
Table 6.8 shows the Receive AC timing parameters. See Figure 6.4 through Figure 6.8 for the receive timing diagrams. Table 6.8 Receive Timing
Limit Sym t31 Parameter Start of Packet to CRS Assert Delay End of Packet to CRS Deassert Delay Start of Packet to RX_DV Assert Delay End of Packet to RX_DV Deassert Delay RX_CLK to RX_DV, RXD, RX_ER Delay RX_CLK High Time RX_CLK Low Time 8 80 18 180 t39 18 180 t40 SOI Pulse Minimum Width Required for Idle Detection 125 20 200 20 200 130 Min Typ Max 200 700 t32 240 600 240 3600 280 1000 8 80 22 600 22 600 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions 100 Mbits/s, MII 10 Mbits/s 100 Mbits/s, MII 10 Mbits/s. relative to start of SOI pulse 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s. relative to start of SOI pulse 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s 10 Mbits/s measure TPI from last zero cross to 0.3 V point.
t33
t34
t37
t38
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-11
Table 6.8
Receive Timing (Cont.)
Limit
Sym t41
Parameter Receive Input Jitter
Min
Typ
Max 3.0 13.5
Unit ns pk
Conditions pk 100 Mbits/s 10 Mbits/s PLEDn Programmed for Activity PLEDn Programmed for Activity
ns pk -pk ms ms ns
t43 t44 t45
PLEDn Delay Time PLEDn Pulse Width RX_CLK, RXD, CRC, RX_DV, RX_ER Output Rise and Fall Times RX_EN Deassert to Rcv MII Output HI-Z Delay RX_EN Assert to Rcv MII Output Active Delay 80
25 105 10
t46
40
ns
t47
40
ns
6-12
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 6.4
MI 100 Mbits/s TPI
IDLE
Receive Timing, Start of Packet (100 Mbits/s)
J
K
DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
DATA DATA DATA DATA DATA
t31 CRS t38 RX_CLK
TX TX TX TX TX
t41
t39
RX
RX
RX
RX
RX
RX
t37 t33 RX_DV t37 RXD[3:0]
PREAMBLE PREAMBLE PREAMBLE PREAMBLE PREAMBLE
t37 RX_ER t43 PLEDn t44
t37
Figure 6.5
MI 100 Mbits/s TPI FXI
DATA
Receive Timing, End of Packet (100 Mbits/s)
T
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
t32 CRS t39 t38 RX_CLK
RX RX RX RX RX RX RX RX TX TX
t37 t34 RX_DV
RXD[3:0]
DATA
DATA
DATA
DATA
DATA
DATA
DATA
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-13
Figure 6.6
MI 10 Mbits/s
Receive Timing, Start of Packet (10 Mbits/s)
t41 TPI t31 CRS t38 RX_CLK
TX TX TX TX TX DATA DATA
t39
RX
RX
RX
RX
RX
RX
t33 RX_DV
t37
t37 RXD[3:0]
PREAMBLE PREAMBLE
DATA
DATA
DATA
RX_ER t43 PLEDn t44
6-14
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 6.7
MI 10 Mbits/s
Receive Timing, End of Packet (10 Mbits/s)
t41 TPI
DATA DATA DATA DATA DATA
SOI
t40 CRS
t32
t38 RX_CLK
RX RX RX RX RX RX RX RX
t39
TX TX
t34 RX_DV
t37
RXD[3:0]
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 6.8
RX_EN RX_CLK RXD[3:0] RX_DV RX_ER COL
RX_EN Timing
t46
t47
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-15
6.3.4 Collision and JAM Timing Characteristics
Table 6.9 shows the Collision and JAM timing parameters. See Figure 6.9 through Figure 6.13 for the associated timing diagrams.
Table 6.9
Collision and Jam Timing
Limit
Sym t51
Parameter Rcv Packet Start to COL Assert Time Rcv Packet Stop to COL Deassert Time Xmt Packet Start to COL Assert Time Xmt Packet Stop to COL Deassert Time PLEDn Delay Time PLEDn Pulse Width Collision Test Assert Time Collision Test Deassert Time CRS Assert to Transmit JAM Packet Start During JAM COL Rise and Fall Time
Min
Typ
Max 200 700
Unit ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns
Conditions 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s 100 Mbits/s 10 Mbits/s PLEDn Programmed for Collision PLEDn Programmed for Collision
t52
130
240 300
t53
200 700
t54
240 300
t55 t56 t57 t58 t591
25 80 105 5120 40 300 800 10
100 Mbits/s 10 Mbits/s
t601
1. Timing not shown
6-16
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 6.9
MI 100 Mbits/s TPO FXO
I
Collision Timing, Receive (100 Mbits/s)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
TPI
I
I
I
I
J
K
DATA
DATA
DATA
DATA
T
R
I
I
t51 COL t55 PLEDn t56
t52
Figure 6.10 Collision Timing, Receive (10 Mbits/s)
MI 10 Mbits/s TPO
TPI t51 COL t55 PLEDn t56 t52
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-17
Figure 6.11 Collision Timing, Transmit (100 Mbits/s)
MI 100 Mbits/s TPI FXI
I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
TPO FXO
I
I
I
I
J
K
DATA
DATA
DATA
DATA
T
R
I
I
t53 COL t55 PLEDn t56
t54
Figure 6.12 Collision Timing, Transmit (10 Mbits/s)
MI 10 Mbits/s TPI
TPO t53 COL t55 PLEDn t56 t54
Figure 6.13 Collision Test Timing
TX_EN t57 COL t58
6-18
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6.3.5 Link Pulse Timing Characteristics
Table 6.10 shows the Link Pulse AC timing parameters. See Figure 6.14 and Figure 6.15 for the Link Pulse timing diagrams. Table 6.10 Link Pulse Timing
Limit Sym t61 t62 t63 t64 Parameter NLP Transmit Link Pulse Width NLP Transmit Link Pulse Period NLP Receive Link Pulse Width Required for Detection NLP Receive Link Pulse Minimum Period Required for Detection NLP Receive Link Pulse Maximum Period Required for Detection NLP Receive Link Pulses Required to Exit Link Fail State FLP Transmit Link Pulse Width FLP Transmit Clock Pulse to Data Pulse Period FLP Transmit Clock Pulse to Clock Pulse Period FLP Transmit Link Pulse Burst Period FLP Receive Link Pulse Width Required for Detection FLP Receive Link Pulse Minimum Period Required for Clock Pulse Detection 8 50 6 7 Min Typ See Figure 2.7 24 Max Unit ns ms ns ms link_test_min Condition
t65
50
150
ms
link_test_max
t66
3
3
3
Link Pulses ns ms ms ms ns
lc_max
t67 t68 t69 t70 t71 t72
100 55.5 111 8 50 5 62.5 125
150 69.5 139 22
interval_timer
transmit_link_burst _timer
25
ms
p_test_min_timer
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-19
Table 6.10
Link Pulse Timing (Cont.)
Limit
Sym t73
Parameter FLP Receive Link Pulse Maximum Period Required For Clock Pulse Detection FLP Receive Link Pulse Minimum Period Required For Data Pulse Detection FLP Receive Link Pulse Maximum Period Required For Data Pulse Detection FLP Receive Link Pulses Required To Detect Valid FLP Burst FLP Receive Link Pulse Burst Minimum Period Required For Detection FLP Receive Link Pulse Burst Maximum Period Required For Detection FLP Receive Link Pulses Bursts Required To Detect AutoNegotiation Capability FLP Receive Acknowledge Fail Period FLP Transmit Renegotiate Link Fail Period NLP Receive Link Pulse Maximum Period Required For Detection After FLP Negotiation Has Completed
Min 165
Typ
Max 185
Unit ms
Condition p_test_max_timer
t74
15
47
ms
data_detect_min_ timer data_detect_max_ timer
t75
78
100
ms
t76
17
17
Link Pulses ms nlp_test_min_timer
t77
5
7
t78
50
150
ms
nlp_test_max_ timer
t79
3
3
3
Link Pulse ms ms ms break_link_timer link_fail_inhibit_ timer
t80 t81 t82
1200 1200 750
1500 1500 1000
6-20
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 6.10
Link Pulse Timing (Cont.)
Limit
Sym t73
Parameter FLP Receive Link Pulse Maximum Period Required For Clock Pulse Detection FLP Receive Link Pulse Minimum Period Required For Data Pulse Detection FLP Receive Link Pulse Maximum Period Required For Data Pulse Detection FLP Receive Link Pulses Required To Detect Valid FLP Burst FLP Receive Link Pulse Burst Minimum Period Required For Detection FLP Receive Link Pulse Burst Maximum Period Required For Detection FLP Receive Link Pulses Bursts Required To Detect AutoNegotiation Capability FLP Receive Acknowledge Fail Period FLP Transmit Renegotiate Link Fail Period NLP Receive Link Pulse Maximum Period Required For Detection After FLP Negotiation Has Completed
Min 165
Typ
Max 185
Unit ms
Condition p_test_max_timer
t74
15
47
ms
data_detect_min_ timer data_detect_max_ timer
t75
78
100
ms
t76
17
17
Link Pulses ms nlp_test_min_timer
t77
5
7
t78
50
150
ms
nlp_test_max_ timer
t79
3
3
3
Link Pulse ms ms ms break_link_timer link_fail_inhibit_ timer
t80 t81 t82
1200 1200 750
1500 1500 1000
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-21
Table 6.10
Link Pulse Timing (Cont.)
Limit
Sym t73
Parameter FLP Receive Link Pulse Maximum Period Required For Clock Pulse Detection FLP Receive Link Pulse Minimum Period Required For Data Pulse Detection FLP Receive Link Pulse Maximum Period Required For Data Pulse Detection FLP Receive Link Pulses Required To Detect Valid FLP Burst FLP Receive Link Pulse Burst Minimum Period Required For Detection FLP Receive Link Pulse Burst Maximum Period Required For Detection FLP Receive Link Pulses Bursts Required To Detect AutoNegotiation Capability FLP Receive Acknowledge Fail Period FLP Transmit Renegotiate Link Fail Period NLP Receive Link Pulse Maximum Period Required For Detection After FLP Negotiation Has Completed
Min 165
Typ
Max 185
Unit ms
Condition p_test_max_timer
t74
15
47
ms
data_detect_min_ timer data_detect_max_ timer
t75
78
100
ms
t76
17
17
Link Pulses ms nlp_test_min_timer
t77
5
7
t78
50
150
ms
nlp_test_max_ timer
t79
3
3
3
Link Pulse ms ms ms break_link_timer link_fail_inhibit_ timer
t80 t81 t82
1200 1200 750
1500 1500 1000
6-22
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 6.14 NLP Link Pulse Timing
a. Transmit NLP TPO t61 t62
b. Receive NLP TPI t63 t64 PLEDn t65 t66
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-23
Figure 6.15 FLP Link Pulse Timing
a. Transmit FLP and Transmit FLP Burst
CLK TPO DATA CLK DATA CLK CLK DATA
t67 t68 t69
t 70
b. Receive FLP
CLK DATA CLK DATA
TPI t71 t72 t73 t74 t75 c. Receive FLP Burst TPI t77 LEDn t78 t79
31.25 62.50 93.75 125.00 156.25
6-24
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6.3.6 Jabber Timing Characteristics
Table 6.11 shows the Jabber AC timing parameters. See Figure 6.16 for the Jabber timing diagram. Table 6.11 Jabber Timing
Limit Sym t91 t92 Parameter Jabber Activation Delay Time Jabber Deactivation Delay Time Min 50 250 Typ Max 100 750 Unit ms ms Conditions 10 Mbits/s 10 Mbits/s
Figure 6.16 Jabber Timing
MI 100 Mbits/s MI 10 Mbits/s TXEN t91 TPO t91 COL t91 CRS t92 Not applicable
AC Electrical Characteristics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-25
6.3.7 MI Serial Port Timing Characteristics
Table 6.12 shows the MI Serial Port AC timing parameters. See Figure 6.17 for the associated timing diagram.
Table 6.12
MI Serial Port Timing
Limit
Sym t101 t102 t103 t104 t105 t106 t107 t108
Parameter MDC High Time MDC Low Time MDIO Setup Time MDIO Hold Time MDC To MDIO Delay MDIO Hi-Z To Active Delay MDIO Active To HI-Z Delay Frame Delimiter (Idle)
Min 20 20 10 10
Typ
Max
Unit ns ns ns ns
Conditions
Write Bits Write Bits Read Bits Write-Read Bit Transition Read-Write Bit Transition Number of consecutive MDC clocks with MDIO = 1
20 20 20 32
ns ns ns Clocks
Figure 6.17 MI Serial Port Timing
t101 MDC
0 1 13 14 15 16
t102
17 30 31
t103 MDIO (READ)
ST1
t104 t106
ST0
REGAD0
t105
TA0 TA1 D15 D14
t107
D0
t103 MDIO (WRITE)
ST1
t104
ST0
REGAD0
TA1
TA0
D15
D1
D0
6-26
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6.4 Pinouts and Package Drawings
This section contains the alphabetical and numerical pin listings for the L80227 as well as its pinouts and package drawing.
6.4.1 L80227 Pinouts
Table 6.13 and Table 6.14 contain the list of L80227 signals. The rst table lists the signals by category and the second lists them by pin number. Table 6.13
Pin Name Media Interface REXT TPI TPI+ TPO TPO+ Controller Interface CRS OSCIN RX_CLK RX_DV RX_EN RX_ER RXD0 RXD1 RXD2 RXD3 TX_CLK TX_EN TX_ER 13 42 26 14 27 18 22 21 20 19 34 40 39 Carrier Sense Output Clock Oscillator Input Receive Clock Output Receive Data Valid Output Receive Enable Input Receive Error Output Receive Data Output Receive Data Output Receive Data Output Receive Data Output Transmit Clock Output Transmit Enable Input Transmit Error Input 50 59 58 55 54 Transmit Current Set Twisted Pair Receive Input, Negative Twisted Pair Receive Input, Positive Twisted Pair Transmit Output, Negative Twisted Pair Transmit Output, Positive
L80227 Pin List (by Signal Category)
Pin Number Description
Pinouts and Package Drawings
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-27
Table 6.13
Pin Name TXD0 TXD1 TXD2 TXD3
L80227 Pin List (by Signal Category) (Cont.)
Pin Number 35 36 37 38 Description Transmit Data Input Transmit Data Input Transmit Data Input Transmit Data Input
Management Interface (MI) MDC MDA4n MDIO PLED0n/MDA0n PLED1n/MDA1n PLED2n/MDA2n PLED3n/MDA3n LEDs PLED4n PLED5n Miscellaneous ANEG COL DPLX SPEED NC NC NC NC NC NC NC NC 30 12 29 28 1 5 15 16 17 24 33 43 AutoNegotiation Control Input Collision Output Full/Half-Duplex Select Input Speed Select Input No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect 2 63 Transmit LED Output Receive LED Output 10 9 11 61 62 3 4 Management Interface (MI) Clock Input Management Interface Address Input Management Interface (MI) Data Input/Output Programmable LED Output/Management Interface Address Input Programmable LED Output/Management Interface Address Input Programmable LED Output/Management Interface Address Input Programmable LED Output/Management Interface Address Input
6-28
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 6.13
Pin Name NC NC NC NC NC NC NC RESETn Power VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 Ground GND1 GND2 GND3 GND4 GND5 GND6 GND7
L80227 Pin List (by Signal Category) (Cont.)
Pin Number 45 46 47 48 49 51 64 44 Description No Connect No Connect No Connect No Connect No Connect No Connect No Connect Reset Input
56 57 7 8 25 32
Positive Supply. 3.3 V 5% Volts Positive Supply. 3.3 V 5% Volts Positive Supply. 3.3 V 5% Volts Positive Supply. 3.3 V 5% Volts Positive Supply. 3.3 V 5% Volts Positive Supply. 3.3 V 5% Volts
52 60 6 41 23 31 53
Ground Ground Ground Ground Ground Ground Ground
Pinouts and Package Drawings
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-29
.
Table 6.14
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
L80227 Pin List (by Pin Number)
Pin Name NC PLED4n PLED2n/MDA2n PLED3n/MDA3n NC GND3 VDD3 VDD4 MDA4n MDC MDIO COL CRS RX_DV NC NC NC RX_ER RXD3 RXD2 RXD1 RXD0 GND5 NC
Description No Connect Transmit LED Output Programmable LED Output/Management Interface Address Input Programmable LED Output/Management Interface Address Input No Connect Ground Positive Supply. 3.3 V Positive Supply. 3.3 V 5% Volts 5% Volts
Management Interface Address Input Management Interface (MI) Clock Input Management Interface (MI) Data Input/Output Collision Output Carrier Sense Output Receive Data Valid Output No Connect No Connect No Connect Receive Error Output Receive Data Output Receive Data Output Receive Data Output Receive Data Output Ground No Connect
6-30
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 6.14
Pin Number 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
L80227 Pin List (by Pin Number) (Cont.)
Pin Name VDD5 RX_CLK RX_EN SPEED DPLX ANEG GND6 VDD6 NC TX_CLK TXD0 TXD1 TXD2 TXD3 TX_ER TX_EN GND4 OSCIN NC RESETn NC NC NC NC NC
Description Positive Supply. 3.3 V Receive Clock Output Receive Enable Input Speed Select Input Full/Half-Duplex Select Input AutoNegotiation Control Input Ground 0 Volts Positive Supply. 3.3 V No Connect Transmit Clock Output Transmit Data Input Transmit Data Input Transmit Data Input Transmit Data Input Transmit Error Input Transmit Enable Input Ground Clock Oscillator Input No Connect Reset Input No Connect No Connect No Connect No Connect No Connect 5% Volts 5% Volts
Pinouts and Package Drawings
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6-31
Table 6.14
Pin Number 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
L80227 Pin List (by Pin Number) (Cont.)
Pin Name REXT NC GND1 GND7 TPO+ TPO VDD1 VDD2 TPI+ TPI GND2 PLED0n/MDA0n PLED1n/MDA1n PLED5n NC
Description Transmit Current Set No Connect Ground Ground Twisted Pair Transmit Output, Positive Twisted Pair Transmit Output, Negative Positive Supply. 3.3 V Positive Supply. 3.3 V 5% Volts 5% Volts
Twisted Pair Receive Input, Positive Twisted Pair Receive Input, Negative Ground Programmable LED Output/Management Interface Address Input Programmable LED Output/Management Interface Address Input Receive LED Output No Connect
6-32
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
6.4.2 L80227 Pin Layout
Figure 6.18 shows the pin layout for the L80227 package. Figure 6.18 L80227 64-Pin LQFP, Top View
NC PLED4n PLED2n/MDA2n PLED3n/MDA3n NC GND3 VDD3 VDD4 MDA4n MDC MDIO COL CRS RX_DV NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC PLED5n PLED1n/MDA1n PLED0n /MDA0n GND2 TPI TPI VDD2 VDD1 TPO TPO GND7 GND1 NC REXT NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
L80227 64-Pin LQFP Top View
NC NC NC NC RESETn NC OSCIN GND4 TX_EN TX_ER TXD3 TXD2 TXD1 TXD0 TX_CLK NC
NC RX_ER RXD3 RXD2 RXD1 RXD0 GND5 NC VDD5 RX_CLK RX_EN
SPEED DPLX ANEG
1. NC pins are not connected.
Pinouts and Package Drawings
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
GND6 VDD6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
6-33
6.5 Mechanical Drawing
This section contains the mechanical drawing for the L80227 64-pin LQFP package. Figure 6.19 64-Pin LQFP Package Drawing
ccc
D
A
Pin 1 See Detail A
See b Detail B
LSI L80227
e
E
D1
Dimension Table Symbol Dimensions b e
E1
0.17 - 0.27 0.50 Basic Max. 0.08 Max. 0.08 11.85 - 12.15 11.85 - 12.15 0.45 - 0.75 1.0 Ref 0.08 - 0.20 Min. 0.08 Max. 1.60 0.05 - 0.15 1.292 - 1.508 0.09 - 0.20 9.90 - 10.10 9.90 - 10.10 0 -7 Min. 0 12
ccc ddd D E L L1 R
ddd R b c @2 Detail B A2 A Detail A @1 R1
@ L
R1 A
L1
A1 A2 c D1
A1
E1 @ @1 @2
Notes 1. All dimensions are in millimeters. 2. Dimensions do not include mold flash. Maximum allowable flash is 0.25. 3. All leads are coplanar to a tolerance of 0.08 (ccc). Bent leads to a tolerance of 0.08 (ddd).
6-34
Specications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Appendix A Application Information
This appendix contains application information for the device. It contains the following sections: Section A.1, "Example Schematics" Section A.2, "TP Transmit Interface" Section A.3, "TP Receive Interface" Section A.4, "TP Transmit Output Current Set" Section A.5, "Transmitter Droop" Section A.6, "MII Controller Interface" Section A.7, "Repeater Applications" Section A.8, "Serial Port" Section A.9, "Oscillator" Section A.10, "LED Drivers" Section A.11, "Power Supply Decoupling"
A.1 Example Schematics
A typical example schematic of the L80227 used in an network interface adapter card application is shown in Figure A.1; a typical switching port application is shown in Figure A.2; and an external PHY application is shown in Figure A.3.
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A-1
Figure A.1
Typical Network Interface Adapter Card Schematic Using the L80227
LSI L80C300 or Equivalent
VDD [4:1] TX_CLK TX_D3 TX_D2 TX_D1 TX_D0 TX_EN TX_ER COL RX_CLK RXD3 RXD2 RXD1 RXD0 CRS RX_DV RX_ER MDC MDIO
50 1% TPO
50 1% 1:1 1 RJ45
System Bus
Bus Interface
10/100 Mbits/s Ethernet Controller
TPO 75 1:1 25 1% TPI 25 1% 75 0.01 75
2 4 5 7 8 3
6
L80227
Optional To system Reset or Float RX_EN RESETn TPI LED 6X Optional 500 6 PLED[5:0]n REXT 25 MHz System Clock OSCIN 10 K 1% 25 1% 25 1%
75
0.01 2 KV
GND [6:1]
A-2
Application Information
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure A.2
Typical Switching Port Schematic Using L80227
LSI L84302 or Equivalent
VDD [4:1] TX_CLK TXD3 TXD2 TXD1 TXD0 TX_EN TX_ER COL RX_CLK RXD3 RXD2 RXD1 RXD0 CRS RX_DV RX_ER MDC MDIO
50 1% TPO
50 1% 1:1 1
RJ45
TPO 75 1:1 25 1% TPI 25 1% 0.01 75 75 75 6 2 4 5 7 8 3
Switch Fabric
10/100 Mbits/s Ethernet Controller
L80227
Optional To system Reset or Float RX_EN RESETn TPI LED 4X Optional 500 4 LED 2X Optional 500 2 50K PLED[1:0]n PLED[5:2]n REXT 10 K 1% 25 1% 25 1%
0.01 2 KV
25 MHz System Clock
OSCIN GND [6:1]
Example Schematics
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A-3
Figure A.3
Typical External PHY Schematic Using L80227
24.9 1%
1.5 K 5%
VDD [4:1] TX_CLK TXD3 TXD2 TXD1 TXD0 TX_EN TX_ER COL RX_CLK RXD3 RXD2 RXD1 RXD0 CRS RX_DV RX_ER MDC MDIO
50 1% TPO
50 1% 1:1 1
RJ45
TPO 75 1:1 25 1% TPI 25 1% 0.01 75 75 75 6 2 4 5 7 8 3
MII Connectors
L80227
Optional Optional 25 1% RX_EN TPI RESETn 25 1% LED 6X Optional 500 REXT 6 PLED[5:0]n 10 K 1% 0.01 2 KV
25 MHz System Clock
OSCIN
GND [6:1]
A-4
Application Information
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A.2 TP Transmit Interface
The interface between the TP outputs on TPO and the twisted pair cable is typically transformer coupled and terminated with the two resistors as shown in Figure A.1 through Figure A.3. The transformer for the transmitter should have a winding ratio of 1:1 with a center tap on the primary winding tied to VDD, as shown in Figure A.1 through Figure A.3. The specications for the transformer are shown in Table A.1. Sources for the transformer are listed in Table A.2. Table A.1 TP Transformer Specication
Specication Parameter Turns Ratio Inductance, ( HMin) Leakage Inductance, ( H) Capacitance (pF Max) DC Resistance ( Max) Transmit 1:1 CT 350 0.05-0.15 15 0.4 Receive 1:1 350 0.0-0.2 15 0.4
Table A.2
Vendor PULSE BEL HALO PCA MIDCOM
TP Transformer Sources1
Part Number H1089, H1102 S558-5999-J9, 558-5999-46 TG22-3506ND TG110-S050N2 EPF8017GH mod2TM technology 05102
1. H1089, S558-5999-46, EPF8017GH and TG22-3506ND are pin compatible. Please contact the transformer vendor for additional information. 2. RJ-45 connector with integrated magnetics and LEDs
The transmit output must be terminated with two external termination resistors to meet the output impedance and return loss requirements of
TP Transmit Interface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A-5
IEEE 802.3. These two external resistors must be connected between VDD and each of the TPO outputs. Their value should be chosen to provide the correct termination impedance when looking back through the transformer from the twisted-pair cable, as shown in Figure A.1 through Figure A.3. The value of these two external termination resistors depends on the type of cable the device drives. To minimize common-mode output noise and to aid in meeting radiated emissions requirements, it may be necessary to add a common-mode choke on the transmit outputs as well as add common-mode bundle termination. The qualied transformers mentioned in Table A.2 all contain common-mode chokes along with the transformers on both the transmit and receive sides, as shown in Figure A.1 through Figure A.3. commonmode bundle termination may be needed and can be achieved when the unused pairs in the RJ45 connector are connected to chassis ground through 75 ohm resistors and a 0.01 F capacitor, as shown in Figure A.1 through Figure A.3. To minimize noise pickup into the transmit path in a system or on a PCB, the loading on TPO should be minimized, and both outputs should always be loaded equally.
A.3 TP Receive Interface
Receive data is typically transformer coupled into the receive inputs on TPI and terminated with external resistors as shown in Figure A.1 through Figure A.3. The transformer for the receiver should have a winding ratio of 1:1, as shown in Figure A.1 through Figure A.3. The specications for this transformer are shown in Table A.1 and sources for the transformer are listed in Table A.2. The receive input must be terminated with the correct termination impedance to meet the input impedance and return loss requirements of IEEE 802.3. In addition, the receive TP inputs must be attenuated. Both the termination and attenuation is accomplished with four external resistors in series across the TPI inputs, as shown in Figure A.1 through Figure A.3. Each resistor should be 25% of the total series resistance, and the total series resistance should be equal to the characteristic impedance of the cable (100 ohm for UTP). It is also recommended that
A-6
Application Information
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
a 0.01 Fcapacitor be placed between the center of the series resistor string and VDD to provide an AC ground for attenuating common-mode signal at the input. This capacitor is also shown in Figure A.1 through Figure A.3. To minimize common-mode input noise and to aid in meeting susceptibility requirements, it may be necessary to add a common-mode choke on the receive input as well as add common-mode bundle termination. The qualied transformers mentioned in Table A.2 all contain common-mode chokes along with the transformers on both the transmit and receive sides, as shown in Figure A.1 through Figure A.3. commonmode bundle termination may be needed and can be achieved when the receive secondary center tap and the unused pairs in the RJ45 connector are connected to chassis ground through 75-ohm resistors and a 0.01 Fcapacitor, as shown in Figure A.1 through Figure A.3. To minimize noise pickup into the receive path in a system or on a PCB, loading on TPI+/ should be minimized and both inputs should be loaded equally.
A.4 TP Transmit Output Current Set
The TPO output current level is set with an external resistor connected between the REXT pin and GND. This output current is determined from the following equation, where R is the value of REXT: Iout Where
Iref = 40 mA (100 Mbits/s, UTP) = 32.6 mA (100 Mbits/s, STP) = 100 mA (10 Mbits/s, UTP) = 81.6 mA (10 Mbits/s, STP)
= (10K/R)
Iref
REXT should typically be a 10 k 1% resistor to meet IEEE 802.3 specied levels. Once REXT is set for the 100 Mbits/s and UTP modes as shown by the equation above, Iref is then automatically changed inside
TP Transmit Output Current Set
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A-7
the device when the 10 Mbits/s mode or UTP120/STP150 modes are selected. Keep REXT as close to the REXT and GND pins as possible to reduce noise pickup into the transmitter. Because the TP output is a current source, capacitive and inductive loading can reduce the output voltage from the ideal level. Thus, in actual application, it might be necessary to adjust the value of the output current to compensate for external loading. One way to adjust the TP output level is to change the value of the external resistor connected to REXT.
A.5 Transmitter Droop
The IEEE 802.3 specication has a transmit output droop requirement for 100BASE-TX. Because the L80227 TP output is a current source, it has no perceptible droop by itself. However, the inductance of the transformer added to the device transmitter output as shown in Figure A.1 through Figure A.3 causes droop to appear at the transmit interface to the TP wire. If the transformer connected to the L80227 outputs meets the requirements of Table A.1, the transmit interface to the TP cable then meets the IEEE 802.3 droop requirements.
A.6 MII Controller Interface
The MII controller interface allows the L80227 to connect to any external Ethernet controller without any glue logic, provided the external Ethernet controller has an MII interface that complies with IEEE 802.3, as shown in Figure A.1 through Figure A.3.
A.6.1 Clocks
Standard Ethernet controllers with an MII use TX_CLK to clock data in on TXD[3:0]. TX_CLK is specied in IEEE 802.3 and on the L80227 to be an output. If a nonstandard controller or other digital device is used to interface to the L80227, there might be a need to clock TXD[3:0] into the L80227 on the edges of an external master clock. The master clock, in this case, would be an input to the L80227. To do this, use OSCIN as
A-8
Application Information
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
the master clock input. Because OSCIN generates TX_CLK inside the L80227, data on TXD[3:0] can be clocked into the L80227 on edges of output clock TX_CLK or input clock OSCIN. In the case where OSCIN is used as the input clock, a crystal is no longer needed on OSCIN, and TX_CLK can be left open or used for some other purpose.
A.6.2 Output Drive
The digital outputs on the L80227 controller signals meet the MII driver characteristics specied in IEEE 802.3 and shown in Figure A.4 if external 24.9 1% termination resistors are added. These termination resistors are only needed if the outputs must drive an MII cable or other transmission line type load, such as in the external PHY application shown in Figure A.3. If the L80227 is used in embedded applications, such as adapter cards and switching hubs (see Figure A.1 and Figure A.2), these terminations resistors are not needed.
MII Controller Interface
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A-9
Figure A.4
MII Output Driver Characteristics
Voh Vol
VDD Rol min = 40 ohm I2 V2 I1 V1 Rol min = 40 ohm V3 I3 loh lol I4 V4
I-V I1, - V1 I2, - V2 I3, - V3 I4, - V4
I (mA) 20 4 4 43
V (Volts) 1.10 2.40 0.40 3.05
A.6.3 MII Disable
Setting the MII disable bit (MII_DIS) in the MI serial port Control register places the MII outputs in the high-impedance state and the disables the MII inputs. When this bit is set to the disable state, the TP outputs are also disabled and transmission is inhibited. The default value of this bit when the device powers up or is reset is dependent on the physical device address. If the device address latched into MDA[3:0]n at reset is 0b1111, it is assumed that the device is being used in applications where there maybe more than one device sharing the MII bus, such as in the use of external PHYs or adapter cards. In this case, the device powers up with the MII interface disabled. If the device address latched into MDA[3:0]n at reset is not 0b1111, it is assumed that the device is being used in application where it is the only device on the MII bus, such as in the use of hubs, so the device powers up with the MII interface enabled.
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Application Information
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A.6.4 Receive Output Enable
The receive output enable pin, RX_EN, forces the receive and collision MII outputs into the high-impedance state. More specically, when RX_EN is deasserted, the RX_CLK, RXD[3:0], RX_DV, RX_ER, and COL pins are placed in a high-impedance state. RX_EN can be used to "wire OR" the outputs of many L80227 devices in multiport applications where only one device may be receiving at a time, such as in a repeater application. Monitoring the CRS pin from each individual port enables the repeater to assert RX_EN only to that L80227 device that is receiving data. The method reduces, by eight per device, the number of pins and PCB traces a repeater core IC requires.
A.7 Repeater Applications
A.7.1 MII Based Repeaters
Using the standard MII as the interface to the repeater core allows the L80227 to be used as the physical interface for MII based repeaters. For most repeaters, it is necessary to disable the internal CRS loopback. For some particular types of repeaters, it may be desirable to either enable or disable AutoNegotiation, force Half-Duplex operation, and enable either 100 Mbits/s or 10 Mbits/s operation. Setting the appropriate bits in the MI serial port Control register can congure these modes. The MII requires 16 signals between the L80227 and a repeater core. The MII signal count to a repeater core is 16 multiplied by the number of ports, which can be quite large. The signal count between the L80227 and a repeater core can be reduced by eight per device if the receive output pins are shared and the RX_EN is used to enable only that port where CRS is asserted. Refer to the Section A.6.4, "Receive Output Enable," page A-11 for more details about RX_EN.
A.7.2 Clocks
Normally, transmit data over the MII is clocked into the L80227 with edges from the TX_CLK output clock. It may be desirable or necessary in some repeater applications to clock in the transmit data from a master
Repeater Applications
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A-11
clock from the repeater core. This requires that transmit data be clocked in on edges of an input clock. The OSCIN input clock is available for clocking in data on TXD. Notice from the timing diagrams that OSCIN generates TX_CLK, and TXD data is clocked in on TX_CLK edges. This means that TXD data is also clocked in on OSCIN edges. Thus, an external clock driving the OSCIN input can also be used as the clock for TXD.
A.8 Serial Port
The L80227 uses an MI serial port to access the device registers. Any external device that has a IEEE 802.3 compliant MI interface can connect directly to the L80227 without any glue logic, as shown in Figure A.1 through Figure A.3. As described earlier, the MI serial port consists of six signals: MDC, MDIO, and MDA[3:0]n. However, only two signals, MDC and MDIO, are needed to shift data in and out. MDA[3:0]n are not needed, but are provided for convenience only. Note that the MDA[3:0]n addresses are inverted inside the L80227 before going to the MI serial port block. This means that the MDAn[3:0] pins would have to be pin strapped to 0b1111 externally to successfully match the MI physical address of 0b00000 on the PHYAD[4:0] bits internally. The MSB of the address is internally tied to zero.
A.8.1 Serial Port Addressing
Tying the MDA[3:0]n pins to the desired value selects the device address for the MI serial port. MDA[3:0]n share the same pins as the LED outputs, respectively, as shown in Figure A.5a. At powerup or reset, the output drivers are 3-stated for an interval called the power-on reset time. During the power-on reset interval, the value on these pins is latched into the device, inverted, and used as the MI serial port address. The PLED[5:2]n outputs are open-drain with a pullup resistor and can drive LEDs tied to VDD. The PLED[1:0]n outputs have both pullup and pulldown driver transistors with a pullup resistor, so the PLED[1:0]n outputs can drive LEDs tied to either VDD or GND.
A-12
Application Information
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
If an LED is to be connected on an LED output, an LED and resistor are tied to VDD as shown in Figure A.4b. To set an address bit HIGH, the LED to VDD connection automatically makes the latched address value a HIGH.To set an address bit LOW, a 50 K resistor to GND must be added as shown in Figure A.4b. If no LEDs are needed on the LED outputs, the selection of addresses can be done as shown in Figure A.4c. To set an address bit HIGH, the pin should be tied to VDD. The pin is HIGH during power-on reset time and latches in a HIGH address value. If a LOW address is desired, the LED output pins should be tied through a 50 K resistor to GND. Figure A.5 Serial Device Port Address Selection
a. Output Driver/Input Address Correspondence
PLED3n PLED2n PLED1n PLED0n MDA3n MDA2n MDA1n MDA0n
b. Setting Address with LEDs
High Low
LED 500 PLED[3:0]n
LED 500 PLED[3:0]n 50K
c. Setting Address without LEDs
High Tie to VDD 50K Low PLED[1:0]n
Serial Port
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
A-13
A.9 Oscillator
The L80227 requires a 25 MHz reference frequency for internal signal generation. This 25 MHz reference frequency can be generated from an external 25 MHz crystal connected between OSCIN and GND or from applying an external 25 MHz clock to OSCIN. If a crystal oscillator is used, it must be a high-capacitance crystal, such as the Abracon ABLS or ABLS2, and it can be added between the OSCIN pin and GND, as shown in Figure A.6. Figure A.6 Connecting the L80227 to a High-Capacitance Crystal
OSCIN 25 MHz
L80227
If a non high-capacitance crystal is used, a 47-pF capacitor must be added between the crystal and GND, as shown in Figure A.7. Figure A.7 Connecting the L80227 to a Non High-Capacitance Crystal
OSCIN 25 MHz 47 pF
L80227
The reason for using a 47 pF capacitor is that the resonant frequency depends on the load capacitance the crystal sees. Because the chip load capacitance is fairly high (around 30 pF), a capacitor in series with the crystal shifts the frequency back to the desired value, Adding a serial capacitor is a robust and practical approach to solving any frequency offset problem without degrading oscillator performance.
A-14
Application Information
Copyright (c) 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
If a non high-capacitance crystal is used, it must have the characteristics shown in Table A.3, and a series capacitor must be added as shown in Figure A.7. The crystal must be placed as close as possible to the OSCIN and GND pins so that parasitics on OSCIN are kept to a minimum. Table A.3
Parameter Type Frequency Equivalent Series Resistance Load Capacitance Case Capacitance Power Dissipation
Non High-Capacitance Crystal Specications
Spec Parallel Resonant 25 MHz 40 max 0.01%
18 pF typical 7 pF maximum 1 mW maximum
A.10 LED Drivers
The PLED[5:0]n outputs can all drive LEDs tied to VDD as shown in Figure A.1 through Figure A.3. The PLED[1:0]n outputs can drive LEDs tied to either VDD or GND. The PLED[5:0]n outputs can also drive other digital inputs, so they can also be used as digital outputs whose function can be user-dened and controlled through the MI serial port.
A.11 Power Supply Decoupling
There are nine VDD pins on the L80227 and seven GND pins. All the VDD pins should be connected together as closely as possible to the device with a large VDD plane. If the VDD pins vary in potential by even a small amount, noise and latchup can result. The VDD pins should be kept to within 50 mV of each other.
LED Drivers
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A-15
All the GND pins should also be connected together as closely as possible to the device with a large ground plane. If the GND pins vary in potential by even a small amount, noise and latchup can result. The GND pins should be kept to within 50 mV of each other. A 0.01-0.1 F decoupling capacitor should be connected between each VDD/GND set as closely as possible to the device pins, preferably within 0.5 inches. The value should be chosen based on whether the noise from VDD-GND is high- or low-frequency. A conservative approach would be to use two decoupling capacitors on each VDD/GND set, one 0.1 F for low-frequency and one 0.001 Ffor high-frequency noise on the power supply. The VDD connection to the transmit transformer center tap shown in Figure A.1 through Figure A.3 has to be well decoupled to minimize common-mode noise injection from the supply into the twisted-pair cable. It is recommended that a 0.01 F decoupling capacitor be placed between the center tap VDD and the GND plane. This decoupling capacitor should be physically placed as close as possible to the transformer center tap, preferably within 0.5 inches The PCB layout and power supply decoupling discussed above should provide sufcient decoupling to achieve the following when measured at the device: The resultant AC noise voltage measured across each VDD/GND set should be less than 100 mV p-p All VDD pins should be within 50 mV p-p of each other All GND pins should be within 50 mV p-p of each other.
A-16
Application Information
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L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
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